NRND = Not Recommended for New Design
2.5V/3.3V, 500MHz 12 2-to-1 Differential LVPECL Clock Multiplexer
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The PI6C485352 is a high-performance low-skew LVPECL fanout buffer. PI6C485352 features two selectable differential inputs and translates to twelve LVPECL output pairs. The inputs can also be configured to single-ended with external resistor bias circuit. The CLK input accepts LVPECL, LVDS, LVHSTL, SSTL or HCSL signals. The PI6C485352 is ideal for differential to LVPECL translations and/or LVPECL clock distribution.
Typical clock translation and distribution applications are data-communications and telecommunications.
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Function | Buffer |
| Number of Outputs | 10 |
| Output Type(s) | LVPECL |
| Maximum Output Frequency (MHz) | 500 |
| Additive Jitter (ps) | 0.05 |
| Supply Voltage (V) | 2.5, 3.3 |
| Input Type(s) | PECL |
| Skew (ps) | 100 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2654 | 2024-02-15 | 2024-04-28 | Device End of Life (EOL) |
| PCN-2602 | 2023-01-31 | 2023-07-31 | Device End of Life (EOL) |
