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Yes, the clock ICs’ outputs can be just left open if they are not used. In this way can save the un-used buffer output drawing power without driving anything.
It is recommended to use 4.7k for pull-up and 1k for pull-down even though Clock IC has internal pull-up/down as high reliability design guide, include un-used inputs pins.
FCP is Frequency Control Product. They include crystals, crystal oscillators (XO), voltage control oscillators (VCXO), and TCXO. XO has IC and crystal integrated together as a component for quality easy use in system designs. For more product information, please visit company website: https://www.diodes.com/products/connectivity-and-timing/crystal-and-crystal-oscillator/
PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs. HiFlex Clock FInder tool
HiFlex XO is programmable frequency synthesis crystal oscillator family. It has very short lead time for any frequency design need,even in flexible quantity. They are specially good for Telecom, Datacom, Ethernet, and SDRAM controller low jitter reference clock designs. HiFlex XO Finder
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.