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Yes. Under any Windows OS, one excellent shareware tool is at www.PCItree.de Follow the install directions in the pt_userg.html file. Changes made with this tool are not permanent, so tuning bridge registers is safe and easy.
The BIOS date is important. The bridge counts 225 PCI clocks from the de-assertion of P_RESET# to the first allowable PCI config cycle, per PCI Spec 2.2**. This is 33 million clocks, about 1 full second at 33 MHz. For BIOS made according to Intel/Microsoft AC97 ("green PC") specification, this 1 second (at 33 MHz) delay is not a problem. But for older BIOS standard, this will block BIOS from enumerating the PCI devices on the secondary PCI bus and thus they have no resources assigned. Since DOS uses the BIOS for PCI enumeration (enumerate == "detect and assign resources"), a motherboard BIOS older than 1996 years might not detect and allocate resources to devices behind the bridge. When plug and play OS loads (many seconds later), then its first enumeration of the computer will detect our bridge (and the devices behind it). Thus Windows 9x and Windows ME OS will detect the bridge, as will any motherboard modern enough to run Windows 2000 or XP. **This is found at page 128, section 184.108.40.206 "Timing Parameters" PCI specification 2.2 table 4-6, Trhfa "RST# High to First Configuration Access". A workaround exists: Place two diodes, P_RESET# to S1_REQ#6 And P_RESET# to S1_REQ#7 so that as P_RESET# is low the internal arbiter senses S1_REQ#6 and S1_REQ#7 low. The diode blocks normal REQ# assertion from resetting the system, but allows P_RESET# to pull low the corresponding S1_REQ#.
The bridge uses the generic PCI-PCI bridge driver already part of Linux kernel 2.2; there is no need for a Pericom specific driver.
The pci-pci bridge will appear to your OS as two standard PCI-PCI bridges. We require no added device driver for Linux kernel 2.2 and higher; our test under Linux (Red Hat 7.0 on Intel PC) locates, configures, and runs devices behind the bridge.
Yes. Address space is reserved in multiples of 1 Mb for the prefetchable and non-prefetchable memory spaces.
"YES, please refer to the following application notes.
AN219 – GreenPacket PCI Express Packet Switch – Industrial Temperature Support 1.0
AN220 – PI7C9X20303SL-404SL Industrial Temperature Support
AN221 – PI7C9X20303ULA Industrial Temperature Support"
When first powering the chip, either power the core voltage (3.3V) before powering Vio or allow 3.3V and 5V to rise together (as is normal for motherboard power supplies).
No, This is a commercial level grade part only.
Adding a PI3L301D in a Notebook PC to switch the signals from the MAC between the RJ-45 on the Notebook and the RJ-45 in a docking station will remove the need for a MAC populated in the docking station and will reduce the overall system cost.
The phase error is measured from the crosspoint of the input reference signals to the crosspoint of the output signals. For example, Pericom clock driver phase error is measured from CK and CK/ input pins to FBIN and FBIN/ pins. Therefore, all 4 probes of a typical oscilloscope are used.
This bridge has two separate posted write FIFOs or buffers, each with 32 DWords (128 bytes) and one per side (i.e. one on the primary PCI port and one on the secondary PCI port). These two FIFOs are used to store all memory write and memory write invalidate transactions going through the bridge. The bridge will continue to store data (until an internal boundary is met) as long as there is room in the FIFO. Once the bridge has one entry, it will start to empty the FIFO on the other side. For the PI7C8154 , there are two posted write buffers of 32 DWords in each direction in order to accommodate the 64-bit data path (thus 256 bytes of data in each direction).
A full detail explanation and product guidelines for memory modules and DDR applications can be found in our Applications section under Memory Modules.
Yes, This part is 3.3V core, but signaling can be at 3.3V or 5V. Two signals are involved P_VIO and S_VIO, according to what these two signals are driven to. The specific primary or secondary bus will be driving either 3.3V signaling or 5V signaling. The input is also 5V tolerant.
This bridge is designed to Intel 21154BE capabilities (power management support at pin D11, 2KV ESD rating, 0.35 micron process, and more robust tolerances for 3.3V/5V power start up sequence.) The bridge also can be used in designs intended for 21154 versions AC, AE, and BC also.
Detect the address of the PCI bridge (since the address will change according to slot on the motherboard and according to the motherboard). Make a PCI type 1 Config Read at the above bus/device/function=0/offset=0C with size of 1 Dword.Use the AND operation: (with the above Dword AND FFFFFF00h).So that bits [0 to 7] are cleared to 0. Use PCI type 1 configuration write to write the new value to bus/device/function=0/offset=0C.That is the entire modification needed.
It is proven by many real application cases that the short propagation delay is the key parameter for a high-speed DDR register. It was seen that even if a 100ps longer propagation from a register failed the DDR module, the shorter the better. In a high-speed DDR module, there is very little margin left for setup time due to the short duty cycle at high-speed, but also the RC delay from many memory chips driven by one register driver. Pericom's DDR module register and are the fastest registers in the market, and are the proven "silver bullet" of resolving DDR module timing problems seen in critical timing system at four corner test.
The reference clock DC specifications and AC timing requirements are shown in the table below. More details can be found in "PCI Express Card Electromechanical Specification Revision 1.1", Chap 2.1.3.
MS1 (pin 106 for package MA-208) is pin R16 for the BGA 8150. It is normally connected to VSS. MS0 (pin 155 for package MA-208) is pin B14 for the BGA 8150. It is normally connected to VDD.
These are actually multiplexed pins. By default, we are compatible with the Intel 21150 solution, where pin 155 is VDD, and pin 106 is VSS. In future versions of this chip, changing the setting (pulled HIGH or LOW) on these pins will allow for future features. For now, these optional capabilities are reserved.