3 Output LVPECL Networking Clock Generator
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| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Supply Voltage (V) | 2.5, 3.3 |
| Additive Jitter (ps) | 0.3 |
| Skew (PS) | 25 |
| Maximum Output Frequency (MHz) | 3x 125/ 150/ 156.25/ 200/ 250/ 155.52/ 311.04/ 312.5 MHz |
| Input Type(s) | Crystal, CMOS |
| Output Type(s) | LVPECL |
| Number of Outputs | 3 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
| Supported Frequencies (MHz) | 125, 150, 156.25, 200, 250, 155.52, 311.04, 312.5 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2328 | 2018-04-12 | 2018-10-12 | Device End of Life for tray packaging only |
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
