PCIe 3.0 Packet Switches are Evolving to Address Power- and Performance-Conscious Applications
The PCI Express® (or PCIe®) architecture has become the preferred interconnect standard in server and storage applications. The growing variety of performance-oriented computing demands in cloud infrastructure, edge devices, telecom networks, 5G infrastructure, embedded systems, and mobile applications also rely on PCIe. In addition, the automotive world is turning to PCIe for its ability to connect multiple zonal ECUs that need to share information and sensor data.
While demanding multi-Gbps bandwidth, these applications also need to be frugal with energy. Telecom-network and data-center operators especially are under pressure to cut utility costs and achieve carbon-reduction targets. PCIe meets these requirements, while also providing flexibility to cater for different system architectures and for the many ways systems with multiple processors share memory resources.
Engineered for Flexibility and Efficiency
The PI7C9X3G606GP is a 6-port/6-lane switch that operates in basic fan-out mode with one upstream and five downstream ports allowing x1 or x2 lane width. Similarly, the 8-port/8-lane PI7C9X3G808GP allows up to seven downstream ports with configurable upstream and downstream lane widths of x1, x2, or x4. Both switches also support cross-domain end-point (CDEP) and non-transparent bridge equivalent mode, meaning that one port is configured as a CDEP to connect to another host rather than an endpoint. This provides failover redundancy and allows communication between two processors, or between a processor and an intelligent adaptor configured in processor mode. The packet switch allows the two hosts to allocate their own PCIe bus and memory resources, and facilitates packet transfer through resource translation.
Each device possesses four physical direct memory access (DMA) channels, increasing the efficiency of data interactions between the host and endpoints. Each physical channel can be shared by two virtual channels, allowing simultaneous data transfer from up to eight DMA channels to eight pairs of locations. The DMA engine is configured and managed by a software driver running on the hosts connected to the upstream port or CD ports. The DMA engines can be used in multiple applications such as device status collection, peer-to-peer host transfer, and peer-to-peer end-point transfer.
Additional features increasing reliability, availability, and serviceability (RAS) include enhanced and advanced error reporting, data protection and error management, and support for hot plugging and surprise hot removal.
Optimized for Power Savings
With the growing importance of low-power operation for better energy ratings, PCIe specifications must support low-power devices and applications. Among these, latency tolerance reporting (LTR) reduces power while the PCIe interface is active by allowing the host to determine when to service an interrupt from any given device. This gives the opportunity to power-down transceivers when they are inactive. An established set of power states allows granular control over power consumption: L0 defines the power state where the link is working normally; L1 defines when parts of the transceiver logic are turned off; and L2 and L3 define further states as the transceiver is turned fully off and power is removed.
In the lower-power modes (higher L numbers), the resume latency is extended. Hence, to give flexible control over power and latency, L1 contains L1.1 and L1.2 substates where an increasing proportion of the transceiver logic is turned off. In L1.1, the transceiver PLL is turned off, while L1.2 reduces power further still by turning off additional circuits at the cost of increased resume latency. Resumption from L1.1 and L1.2 is faster than from L2. The L0s state is also defined, which allows two devices on a link to power-down their transmitters independently when data is being transferred in only one direction.
The PI7C9X3G606GP and PI7C9X3G808GP devices support these states and substates, and allow the turning off of any empty hot-pluggable ports until needed. With power management schemes for startup and continuous operation, both devices draw very low power in all modes. Under full load and 80°C junction temperature, the PI7C9X3G808GP draws only 2.9W. The devices are specified over the industrial temperature range of -40°C to 85°C.
Additional features of these switches include a built-in PCIe 3.0 clock buffer designed to support low-power operation, and a built-in thermal sensor to report operational temperature instantly. To help designers optimize application functionality and performance, the buffer supports various PCIe 3.0 reference clock architectures including common, separate reference no spread (SRNS), and separate reference independent spread (SRIS).
The switches also support advanced PCIe features, such as access control service (ACS), multi-cast, atomic operation, alternate routing ID (ARI), and address translation (AT) that assist with traffic management, packet handling, and multi-processor or multi-thread synchronization.
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