訊號標準不斷推陳出新，而電位也持續降低。由於許多產品皆具備雙向功能，並可從 1-bit 擴充至 +32-bit，同時支援 1.5 V 至 5 V 通訊電源，現今的設計工程師發現到，自己定期在尋求解決方案來解決這些混合產品應用之間的通訊問題。Diodes 生產各種可提供混合訊號（TTL、HSTL 及 SSTL）和多重供應電壓轉換（5 V、3.3 V、2.5 V、1.8 V 及 1.2 V） 的IC。
Pericom offers great chip-to-chip interface between different I/O voltages ranging from 1.5/1.8/2.5/3.3 V to 5 V, and 0.8 V to 2.5 V. These translators are scalable from 16-bit to 32-bits and beyond. See following page for product listing.
I/O Signal Translation
These devices provide the ability to convert between different I/O’s (HSTL to LVTTL or LVCMOS, SSTL to TTL, etc.) and are scalable from 12-bit to 32-bit and beyond.
Most ALVC/ALVCH devices are not 5V I/O Tolerant. However, several Pericom ALVCT/ALVCHT devices are 5V I/O Tolerant.
Yes, a logic driver can tolerate heavy undershoot with short duration because there is an ESD diode between the input or output of the driver and ground in reversal direction. This ESD diode will clamp and absorb the undershoot when the undershoot reaches below -0.7V. Please also refer to the maximum ratings specified in the datasheet.
Yes. ALVTC is designed to operate from 1.65V to 3.6V with 2.5V nominal voltage. Thus, ALVTC can be used as standard 1.8V or 3.3V logic as well.
Yes. AVC+ can operate from 1.65V to 3.6V with a 2.5V nominal operating voltage. The wide operating voltage range makes AVC+ suitable for 1.8V, 2.5V or 3.3V operation.
The voltage applied to the VCCA pin can be any voltage in the nominal voltage range, for example, it is ok to apply 2.0V to the VCCA pin of PI74AVC164245, since the 2.0V Vcc falls in the nominal range of the 1.8V to 2.5V.
For many of Pericom's logic drivers, buffers and inverters, it is allowed to shorten a few of the output pins in order to increase the driver strength for heavy resistive or capacitive load, but the maximum current and power consumption must meet the spec of the logic device.
The PI74FCTxx logic devices can accept a 3.3V input as valid high since their spec of Vih is minimum 2.0V. But the PI74FCTxx logic devices can not work at 3.3V Vcc.
When the capacitive load is heavy, higher than 50pf, the RC effect generated by the driver's output impedance, and the capacitive load will override the transmission line effect causing slow edges but will also help to absorb or averaging the overshoot and undershoot. Therefore reduce or even cancel the series termination resistance at the output of the driver from its matching value is essential for faster system time.
The trace impedance can be controlled by the PCB layout design and the PCB manufacturer. Please refer to Application Note 32 for the calculation details.
The driver's output impedance R_out for the NMOS and PMOS are 10-ohm and 20-ohm, use 15-ohm for their averaged output impedance, and then match the 15-ohm with the trace impedance by adding a series termination resistor at the output of the driver: R_out + R_termination = Z_trace. If the trace impedance is 50-ohm, use 35-ohm for the series termination resistor.
LVTC's inputs and outputs are designed with power-up/down control circuits, which senses the device's Vcc supply voltages and put the inputs/outputs in high-impedance during the power up/down stages of live insertion/extraction. This will avoid the backflow of damaging current into the device and through the device to other components, and prevent driver conflict. Application Note 62 for more details.
The max propagation delays for ALVC(H) are from 3.0ns (for buffers) to 5.0ns.
The max propagation delays for AVC+ is from 1.9ns (for buffers) to 3.2ns. It is very fast.
The max. propagation delays for ALVTC ranges from 2.6ns (for buffers) to 4.2ns. It is very fast.
FCT logic devices are offered in several different speed grades: Blank, A, B, C, D and E. For a buffer device, the max. propagation delay for Blank speed is 8.0ns and that for E speed is 3.2ns. Contact factory for availability.
LCX is a high-speed logic family. The max. propagation delay for a buffer device is 4.5ns.
SOTiny Gate ST (1.65 to 3.6V) family has a typical propagation delay of 1.8ns, while the STX (1.65 to 5.5V) family has typical propagation delays from 2.4ns to 3.2ns. They are one of the fastest speed gate logic available in the market.
Most Pericom logic devices can work at a frequency above 133 MHz. Normally, the maximum frequency depends on the timing and switching characteristics such as Tpd, Tsetup, Thold, etc. The maximum frequency also depends on the system condition, including the driver strength, the capacitive load and the trace/cable length, etc. At system level, the best way to determine the maximum frequency is to simulate the IBIS model of the logic device in the system topology.
For the R_on of NMOS: in the IBIS model, find the [pulldown] data in the model_type output or model_type 3-state, calculate the R_out by using the [pulldown] voltage data at 0.5V, but also at Vdd 0.5V, both divided by their current data I(typ), then, averaging the R_out at 0.5V and at Vdd-0.5V for the final R_out. For example, for the R_out of PI6C2510-133EL, download the IBIS model 6c2510el.ibs from Pericom's website, using the data in model_type output (Model 2510E_OUT1), the R_out at 0.5V and at 2.8V (Vdd-0.5V = 2.8V) is: At 0.5V: 0.49841V / 0.0211535A = 23.56-ohm. At 2.8V: 2.79932V / 0.0855804A = 32.71-ohm. The average output impedance R-on for the NMOS is: (23.56-ohm + 32.71-ohm)/2 = 28.13-ohm. The calculation of the PMOS is the same with the NMOS, but using the [pullup] data in the same model of a model_type output. . At 0.5V: |0.498471V / -0.0208299A| = 23.93-ohm. At 2.8V: | 2.79934V / -0.0901073A| = 31.06-ohm. The average output impedance R_on for PMOS is (23.93-ohm + 31.06-ohm)/2 = 27.49-ohm.
The output impedance of the driver plus the series termination resistor at the output of the driver must equal the impedance of the trace: Z_out + Z_termination = Z_trace. For instance, if the Z_trace is 50-ohm and the Z_out is 20-ohm: 20 + Z_termination = 50; Z_termination = 30-ohm. Thus in order to match the impedance of the driver and the trace, we need to add a 30-ohm series termination resistor at the output of the driver.
Heavy Vcc ripple and ground bounce will cause output jitter. Using sufficient bypass (de-coupling) capacitors, recommended 0.47uf and 0.1uf as close to the Vcc pin as possible, will minimize the Vcc ripple and ground bounce. Please refer to application note 24 for more details.
Yes. ALVTC is compatible with ALVT BiCMOS logic. In comparison, ALVTC consumes much less power than ALVT BiCMOS logic.
LCX specifications and performance are very similar to other 3.3V CMOS families in the market, such as LVC, LVX etc. In most applications, LCX and LVC can be used interchangeably.
Yes. LCX logic devices are 5V I/O Tolerant and can be used in a mixed-signal environment.
Yes. LVTC logic has all the required features for "live-insertion" and is compatible with BiCMOS LVT logic.
Yes. LVTC logic devices are 5V I/O Tolerant and can be used in a mixed-voltage environment.
Not all obsolete parts will have a direct replacement. However, we recommended that you contact your regional sales office.
Most gate logic suppliers have multiple gate families that cover different voltage and speed ranges thus increasing the bill of material callouts and inventory cost. Pericom's SOTiny Gate STX family covers broad operating voltage ranges and speeds. The one single family STX provides all customers needs for single, dual, triple gate logic.
ALVC(H) devices usually come with both -24/24mA and -12/12mA balanced drives to suit different application needs. PI74ALVC(H)16xxx are 24mA drive devices while PI74ALVC(H)162xxx are 12mA devices.
FCT logic devices are offered in both high drive (-32/+64mA) and balanced drive (-24/+24mA) to suit different application requirements. The 24mA balanced drive FCT devices have 25-ohm equivalent output resistance built in to match the transmission line impedance, therefore eliminating the need for external termination resistors.
CMOS DDR registers, 2.3V to 2.7V, ultra fast 1.1ns to 2.2ns propagation delay, low power dissipation, low noise, -24/+24mA balanced output drive.
CMOS 2.3V to 3.6V, <3ns propagation delay, low power dissipation, low noise, -12/+12mA or -24/+24mA balanced output drive, 5V tolerance (ALVCT), bus hold (ALVCH). ALVC (Advanced Low-Voltage CMOS) is a very fast 3.3V CMOS logic family. ALVCH has "Bus Hold" on the inputs that eliminates external pull-up/down resistors.
CMOS, 3.3V (FCT3) or 5V (FCT5), 3.2ns to 7ns propagation delay, low power dissipation, -32/+64mA high drive, -12/+12mA or -24/+24mA balanced output drive, bus hold. FCT (Fast CMOS Technology) is a 5V logic family with TTL compatible input and output levels. It's the fastest 5V CMOS logic family available today in the market.
CMOS, 2.0V to 3.6V, 4.5ns propagation delay, low power dissipation, low noise, -24/+24mA balanced output drive, 5V tolerance. LCX (Low Voltage, High-Speed) is a 3.3V widely used high-speed, balanced-drive, lower power and low noise family.
CMOS, 3.3V, 4.1ns propagation delay, low power dissipation, low noise, -24/+24mA balanced output drive, 5V tolerance, bus hold.
CMOS, 2.7V to 3.6V, 3.3ns propagation delay, low power dissipation, low noise, -24/+24mA balanced output drive, bus hold. LVTC (Low Voltage Technology CMOS) is a 3.3V CMOS logic designed for "live-insertion" applications. LVTC power-up/down high-impedance feature protects the components and the main boards from being damaged during live-insertion.
CMOS DDR registers, 2.3V to 2.7V, 1.Xns to 2.8ns propagation delay, low power dissipation, low noise, -24/+24mA balanced output drive.
CMOS, ultra small package, 1.65V to 3.6V (ST) or 1.65V to 5.5V (STX), 1.8ns to 2.4ns propagation delay, low power dissipation, low noise, -24/+24mA or -32/+32mA balanced output drive.
CMOS, 1.8V to 3.6V, <2ns propagation delay, low power dissipation, low noise, -24/+24mA balanced output drive.
There are several types of jitter, but the main ones are: cycle-to-cycle jitter, period jitter, half period jitter, and peak-to-peak jitter. Jitter terminology can be found in AB36: Jitter Measurement Techniques at Application Brief No. 36 or Application Note No. 27.
Leave the unused output pins open; connect the unused sole input pins to Vcc or ground with a trace or a 10K to 100K resistors. For unused I/O pins, if it is set High-Z, connect it to Vcc or ground through a 10K to 100K resistor, or leave it open if it is active.
If the impedance of the trace is higher than the sum of the impedance of the driver and the series termination resistor, overshoot and undershoot will be seen at the input of the receiver on the end of the trace.
If the impedance of the trace is lower than the sum of the impedance of the driver and the series termination resistor, attenuated slower edges will be seen at the input of the receiver on the end of the trace.
"Bus Hold" is a feature of the ALVCH logic family which holds the inputs of devices at their last valid logic state when the drivers go to high-impedance, thus eliminating external pull-up/down resistors.
Hot-plug indicates that the devices, including switches populated on the motherboard (backplane), will turn off the power and signals to the hot-plug connectors during hot insertion, thus, there is no power and signal activity on the connectors while the system is still running. All Pericom switches are suitable for hot-plug.
Hot-swap (live-insertion) indicates that the connectors on the motherboard (backplane) are alive with signal and power during hot-swap. The logic drivers populated on the hot-swap card should tolerate the impact from hot-swap without clamping or distorting the signal from the motherboard. Pericom logic family is suitable for hot-swap. Please refer to the PCI standards "Compact PCI Hot-Swap Specification R1.0", "PCI Hot-Plug specification R1.0" and Pericom Application Brief 39 for more details.
Pericom SOTiny Gate logic consists of single, dual, and triple gate logic devices. These devices have broad operating voltages (1.65V to 5.5V) and very fast speeds (1.8ns to 3.2ns), and come in very small packaging. Pericom offers two SOTiny Gate families: ST (single gate) and STX (single, dual and triple gates).
Compared to a passive switch voltage translator, a logic voltage level shifter can drive longer trace with higher capacitive load at higher frequency, due to its active driving output. It is also capable of translating a voltage level from both high to low, and low to high.
A logic voltage level shifter has longer propagation delay and requests a direction control signal.
An edge control circuit is inside the buffer output circuit for dynamic output impedance which varies dependent on the output voltage for overshoot and undershoot reduction while retaining fast rising and falling edges.
All Pericom's products that are not lead-free are composed of 85% Sn and 15% Pb. For lead-free products, they are composed of 100% matte Sn. Lead-free products are marked and ordered with the letter "E" suffix at the end of the part number.
The maximum voltage is listed in the maximum ratings in the datasheet.
It depends on the frequency and the capacitive load, the higher the frequency and capacitive load, the shorter the maximum trace length. The best way to determine the maximum trace length is to simulate the IBIS model.
The undershoot current is meanly generated by the undershoot going through the ESD diode between the input (or output) to the ground. The ESD diode can tolerate an undershoot current at forwarding direction and with short duration up to 250mA, which exceeds most of the maximum undershoot current, even if it was from a very strong driver.
Due to its characteristics, the maximum working frequency of a logic driver is dependent on many application parameters including the output trace length and the capacitive load. Normally, if the output trace length is less than 4 and the capacitive load is less than 15pf, the maximum working frequency for a logic device can go up to 150MHz-200MHz depending on the device type. But the best way to determine the maximum working frequency is to simulate the IBIS model with a particular application circuit.
It is proven by many real application cases that the short propagation delay is the key parameter for a high-speed DDR register. It was seen that even if a 100ps longer propagation from a register failed the DDR module, the shorter the better. In a high-speed DDR module, there is very little margin left for setup time due to the short duty cycle at high-speed, but also the RC delay from many memory chips driven by one register driver. Pericom's DDR module register and are the fastest registers in the market, and are the proven "silver bullet" of resolving DDR module timing problems seen in critical timing system at four corner test.
LCX has very low noise on its outputs. The typical VOLP (Output Ground Bounce) is less than 0.8V.
It is recommended to use a 0.47uf and a 0.1uf as close to the Vcc pin as possible for Vcc ripple cancellation. Vcc ripples will cause output jitter. Please refer to application note 24 for more details.
Bidirectional level shifters can shift signals between 1.5V, 1.8V, 2.5V and 3.3V. They can also translate between HSTL, SSTL and LVCMOS logic standards.
It is not recommended to use a normal CMOS driver without live-insertion protection circuit because the signal from the motherboard (backplane) applied to the driver output will be forwarded by the parasitic diode in the PMOS to the Vcc at 0V delayed by the bypass capacitance. Please refer to application note 62 and application brief 39 for more details.
LVTC's CMOS design consumes much less power (60% less) than LVT BiCMOS, and costs less than LVT BiCMOS.
FIT and MTBF data can be found at Pericom's Quality webpage.
Lead (Pb)-Free and Green information can be found on individual datasheets or Pb-Free & Green Page.
There are two approaches to obtain the output impedance of a Logic driver: Extract the R-on from the V-I data in the IBIS model (available on the web), which is preferred because it is faster and easier; Or register/login to the website to obtain technical assistance.
The and families are suitable for live-insertion. Please refer to application note 62 for more details.
Otherwise overshoot, undershoot, or attenuation will be seen at the input of the receiver on the end of the trace.
It is for system signal integrity and system timing. IBIS model simulation provides the fast, simple, and accurate PCB timing results for any particular driver and receiver with any combination of frequency, trace length, capacitive load, and other parameters before the PCB is made. This will reduce the system design cycle and prevent the second or third PCB spin as normally seen in old system design approaches without simulation.
ALVTC has high current drive (-32mA/64mA), so as to achieve fast speeds in heavy load applications.
SOTiny Gate logic devices can perform simple logic functions and their tiny packages enable them to be conveniently placed where they are needed. These tiny gates can also provide quick fix to design bugs on board. These benefits make SOTiny Gate logic devices very popular in today's system designs from handheld to large systems.
FCT part number ordering nomenclature is "PI74FCTxxx"+"Speed grade"+"T"+"Package code". However, during the manufacturing process, the "Speed grade" is marked after the "Package code" as "PI74FCTxxx"+"T"+"Package code"+"Speed grade". See the Packaging Support Documentation section of the website for detailed explanation.
The / level shifters will not be damaged if only one of the VCCA or VCCB pins is powered while the other not.