Diodes 的 LVDS（低電壓差動訊號）裝置具備高效能 5 V、3.3 V、2.5 V 及 1.8 V 特性，其傳輸延遲低於 2.0ns，可滿足現今的高速 I/O 介面需求。LVDS 系列產品提供線性驅動器、接收器、收發器、交叉點、時脈 / 資料配送及中繼器，可滿足現今支援 8-bit、16-bit、18-bit 及 32-bit 功能的高速 I/O 介面傳輸需求。
Low Voltage Differential Signaling Technology
Drivers, Receivers, Transceivers, Crosspoints, & Clock/Data Distribution
LVDS for Multi-Function Printers
The traditional way of using TTL signals between the image-scanning module and the image process unit board fails to provide the density data transmission at high speed to provide good signal integrity for printing. LVDS transmission is the best way for the signal to link with high-speed, good signal integrity, and low EMI.
PI90LV017A acts as a LVDS driver supporting transmission data rates exceeding 400 Mbps. The same 8-pin SOIC, TSSOP and MSOP packages support Pericom’s PI90LV027A, and so designers can easily alternate the layout if there is a need for LVDS dual-driver transmission among various models.
Yes. BLVDS, or Bus LVDS is identified with a B in the part number. For instance PI90LVB010
Pericom offers several application documents relating to LVDS devices See the Application Page.
For a 3.3V LVDS driver to drive a 2.5V LVDS receiver, a resistor network is required to change the common mode voltage to meet the specification of the 2.5V LVDS receiver.
For a 3.3V LVDS receiver to accept a 2.5V LVDS signals, the 2.5V signal will need to meet the VID specified in the datasheet of the 3.3V LVDS receiver.
Yes, it is possible to interface LVDS with CML. Please refer to Application note 47.
Yes, it is possible to interface LVDS with LVPECL. Please refer to Application note 47.
Yes, it is possible to interface LVDS with PECL. Please refer to application note 47.
Yes, it is possible to interface LVDS with Single-ended signals. Please refer to Application note 47.
For detailed information regarding to how to interface single-ended signals to LVDS signals, please refer to Application Note 47: Interfacing LVDS to PECL, LVPECL, CML, RS-422 and Signal-Ended Devices.
It is recommended that the device should not operate at 2.5V since it was designed to operate at 3.3V. Operating the device different to what it is specified in the datasheet could lead to system malfunction or reliability issues.
Pericom LVDS devices can operate below the specified data rate on the datasheet. The specified data rate only states the maximum data rate. However, it should be noted that jitter will increase as frequency decreases.
Yes. LVDS only supports point-to-point topology, while BLVDS and M-LVDS are used to support bus and multi-point topologies.
Yes. LVDS requires a 100-ohm +10% differential termination resistor.
LVDS, BLVDS and M-LVDS technologies support live insertion. Note: Live insertion is defined as: Vcc is applied when the cable is disconnected or reconnected.
Currently Pericom does not have a repeater that supports SATA II.
Yes, LVDS devices with an internal termination are marked as PI90LVTxxx.
To measure the jitter of an Eye Pattern, measure at the 0V differential voltage (optimal receiver threshold point) for minimum jitter. Measured at +100mV from the 0V differential to obtain the maximum jitter (worst case). Measuring at the cross point will result in a much lower jitter reading.
LVDS, BLVDS and M-LVDS are all based on the same technology. The differences between the three are: LVDS is used for point-to-point topologies with a 100-ohm termination scheme. BLVDS is used for multi point and backplane topologies with a 50-ohm termination scheme. BLVDS also has a stronger drive strength compared to LVDS to support bus and multi-point topologies. M-LVDS is used for multi-point topologies with a 50-ohm termination scheme. M-LVDS has a stronger drive strength compared to LVDS to support multi-point topologies.
The failsafe features will be asserted if any of the three conditions are met:
The maximum distance for LVDS, as defined in the ANSI/TIA/EIA-644-A, is 10 meters. But by using high quality cables, the actual distance can go beyond 10m. The actual limiting distance for LVDS is application dependent.
Unlike LVDS, which has no defined maximum speed, M-LVDS has a maximum line speed of 500-Mbps defined in the TIA/EIA-899 Standard. The actual speed of M-LVDS is application dependent.
LVDS signal integrity is determined by the Eye Pattern shape and Bit Error Rate (BER) during data transmission.
Pericom Semiconductor marked LVDS device as PI90LVxxx and BLVDS as PI90LVBxxx. Other device top marking information can be found at the Packaging Page.
LVDS is completely different from Serdes (serializer / deserializer). Some SerDes use LVDS signaling as the serial transmission, for instance Pericom's SerDes PI90SD1636 offers LVPECL signaling as the serial transmission.
Yes, LVDS is low noise. This is the result of the differential signaling which allows common-mode noise rejection. When noise is coupled to the common-mode, the receiver will only see the differences in the differential signals and will reject any noise. In addition to the common-mode noise rejection, the voltage swing for LVDS signal is away from Vcc and Ground which will further help minimized noise.
LVDS is low power due to the low 350mV (typical) voltage swing and the current mode design.
LVDS requires a 100-ohm differential termination resistor, whereas Bus LVDS (BLVDS) requires a 50-ohm differential termination resistor.
No. M-LVDS is not defined in the same standard as LVDS. M-LVDS is defined in the TIA/EIA-899 Standard.
Yes, The failsafe features are incorporated into all LVDS receivers.
Not all obsolete parts will have a direct replacement. However, we recommended that you contact your regional sales office.
Pericom offers LVDS drivers and receivers ranging from 1, 2, 4, 10 and 16-bits.
Pericom Semiconductor Corp. offers LVDS drivers, receivers, transceivers, crosspoints, repeaters, and clock/data distribution products.
There are several parameters: slew rates, voltage swing, crosspoints, jitter in Eye Pattern, Bit Error Rate, and others. But the two commonly used parameters are jitter in Eye Patterns and Bit Error Rate Testing (BERT).
CMOS, 2.7V to 3.6V, 3.3ns propagation delay, low power dissipation, low noise, -24/+24mA balanced output drive, bus hold. LVTC (Low Voltage Technology CMOS) is a 3.3V CMOS logic designed for "live-insertion" applications. LVTC power-up/down high-impedance feature protects the components and the main boards from being damaged during live-insertion.
There are several types of jitter, but the main ones are: cycle-to-cycle jitter, period jitter, half period jitter, and peak-to-peak jitter. Jitter terminology can be found in AB36: Jitter Measurement Techniques at Application Brief No. 36 or Application Note No. 27.
Application dependent or application specific means the signal integrity of LVDS depends on the required signals quality. The performance and signal quality of LVDS will depend on the types of equipment and signal quality used. For example, when using a CAT3 cable, an LVDS signal can go no further than 10m. However, using a high quality cable such as CAT5, LVDS signals can go beyond the maximum specified distance. Similar concepts apply to the speed of LVDS signals.
"Bus Hold" is a feature of the ALVCH logic family which holds the inputs of devices at their last valid logic state when the drivers go to high-impedance, thus eliminating external pull-up/down resistors.
BER (Bit Error Rate) Testing, sometimes fully abbreviated as BERT is a testing procedure to determine the quality of the LVDS signals by the number errors over the total number of bits sent. Commonly used BERT are: 1x10e-12 = One or less errors in 1 trillion bits sent or 1x10e-14 = One or less errors in 100 trillion bits sent
Common-mode noise rejection is an inherent feature of true differential receivers. It is the ability to reject noises that are of the same direction and of the same magnitude in differential signals. For example, when a +50mV noise is coupled onto the LVDS receiver's line, both the input+ (normally at 1.375V) and input- (normally at 1.025V) will be raised higher by +50mV resulting in the input+ at 1.425V and input- at 1.075V. But the receiver will ignore the change in voltage, in this case, the 50mV noise since the differences between the input+ and input- is still 350mV. To the LVDS receiver, there has be no disturbance to the LVDS signal.
Hot-plug indicates that the devices, including switches populated on the motherboard (backplane), will turn off the power and signals to the hot-plug connectors during hot insertion, thus, there is no power and signal activity on the connectors while the system is still running. All Pericom switches are suitable for hot-plug.
LVDS stands for Low Voltage Differential Signaling. It is a high speed differential signal with low voltage swing of 350mV typical.
The common-mode range for M-LVDS is typically 1.2V +/- 2V. The LVDS common-mode is typically 1.2V +/-1V.
The common-mode range for LVDS is typically 1.2V +/-1V. This will allow the receivers input to have an operating range from GND to +2.4V. The common-mode range for M-LVDS is typically 1.2V +/-2V.
Commonly used BERT are: 1x10e-12 = One or less errors in 1 trillion bits sent or 1x10e-14 = One or less errors in 100 trillion bits sent.
An edge control circuit is inside the buffer output circuit for dynamic output impedance which varies dependent on the output voltage for overshoot and undershoot reduction while retaining fast rising and falling edges.
Standard Pericom's LVDS devices can meet 10kV HBM-ESD. However, Pericom also offers some specially designed LVDS devices that are designed to meet lower HBM-ESD (For non-standard HBM-ESD, the datasheet will spec this value)
Pericom's LVDS devices will provide an output if a valid differential swing is 5mV or greater.
All Pericom's products that are not lead-free are composed of 85% Sn and 15% Pb. For lead-free products, they are composed of 100% matte Sn. Lead-free products are marked and ordered with the letter "E" suffix at the end of the part number.
It depends on the frequency and the capacitive load, the higher the frequency and capacitive load, the shorter the maximum trace length. The best way to determine the maximum trace length is to simulate the IBIS model.
The output-to-output skew is typically less than 250ps within the same bank of the same device. This applies to most LVDS drivers and distributors. Please refer to the datasheet.
The recommended operating voltage for all Pericom LVDS products is 3.3V +/- 10%.
All Pericom LVDS devices will meet or exceed the TIA-644, which states that the LVDS signal will be able to travel a distance of 10m. Note that the statement also indicates that it is application dependant.
LVDS typical output swing is 350mV.
The PI3L301D is suggested for Gigabit Ethernet applications. The PI3L301D has the lowest combination of both R-on and C-on in the LAN switch market, resulting in lowest return-loss which exceeds the requirement for the IEEE 802.3ab Gigabit PHY conformance tests spec.
There are several types of cables used for LVDS data transfer. Some commonly used cables are: Firewire, CAT3, CAT5, Twin-Ax, Ribbon Cables and others. The quality of the cable is a major factor to be considered if distance is an issue. CAT3 cables are good for about 10 meters, while CAT5 has been used for longer distances. Actual distance for LVDS is application dependent.
A 0.1uF, 0.01uF, and 0.001uF are recommended for decoupling and should be placed as close as possible to the Vcc pin of the device. A bulk capacitor of 10uF 35V tantalum is also recommended for the PCB. The actual number of decoupling capacitors needed will depend on the PCB environment.
A commonly used signal to test LVDS uses a NRZ (non-return-zero) coding scheme with PRBS (pseudo-random bit stream) signals.
Pericom offers 3.3V Vcc for LVDS devices.
FIT and MTBF data can be found at Pericom's Quality webpage.
Lead (Pb)-Free and Green information can be found on individual datasheets or Pb-Free & Green Page.
LVDS Standard can be obtained from the Global Engineering Documents at http://global.ihs.com.
ALVTC has high current drive (-32mA/64mA), so as to achieve fast speeds in heavy load applications.