4-Output Low Power PCIE GEN1-2-3 Buffer
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The PI6CDBL401B is a 4-output low power buffer for 100MHz PCIe Gen1, Gen2 and Gen3 applications with integrated output terminations providing Zo=100Ω. The device has 4 output en- ables for clock management, and 3 selectable SMBus addresses.
PCIe 3.0/2.0/1.0 clock distribution
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Function | PCIe clock buffer |
| Number of Outputs | 4 |
| Output Type(s) | HCSL |
| Maximum Output Frequency (MHz) | 100 |
| Additive Jitter (ps) | 50 |
| Supply Voltage (V) | 3.3 |
| Input Type(s) | HCSL |
| Skew (PS) | 50 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2328 | 2018-04-12 | 2018-10-12 | Device End of Life for tray packaging only |
