11 Outputs HiFlex™ Ethernet Network Clock Generator
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The PI6LC58S1101 is very low jitter clock generator target for applications that demand extremely low phase noise, such as 10GbE, 40GbE, 100GbE, and 400GbE. It uses Diodes' proprietary LC VCO-based PLL design to achieve an optimum combination of those popular networking clock frequencies and low phase noise performance along with high power supply noise rejection.
The PI6LC58S1101 has four output banks which can be configured independently for different frequencies and different output signaling types based on control pins. The pin control method provides an easy way to configure the device at the hardware level.
Compliance (Only Automotive(Q) supports PPAP) | Standard |
---|---|
Supply Voltage (V) | 3.3 |
Jitter RMS (ps) | 0.08 |
Skew (PS) | N/A |
Output Frequency (MHz) | 25, 50, 125, 156.25, 312.5MHz |
Input Type(s) | Crystal |
Output Type(s) | LVPECL, LVDS |
Number of Outputs | 11 |
Ambient or Junction Temperature (°C) | - 40 to 85C |
Supported Frequencies (MHz) | 25, 50, 125, 156.25, 312.5 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs. HiFlex Clock FInder tool
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.