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The PI6LC58S1101 is very low jitter clock generator target for applications that demand extremely low phase noise, such as 10GbE, 40GbE, 100GbE, and 400GbE. It uses Diodes' proprietary LC VCO-based PLL design to achieve an optimum combination of those popular networking clock frequencies and low phase noise performance along with high power supply noise rejection.
The PI6LC58S1101 has four output banks which can be configured independently for different frequencies and different output signaling types based on control pins. The pin control method provides an easy way to configure the device at the hardware level.
3.3V Supply Voltage
Crystal/CMOS Input: 25MHz/50MHz
Differential Input: 25MHz/50MHz
Selectable Output Frequencies
Four Output Banks with Selectable Output Signaling: LVPECL or LVDS
Very low RMS Phase jitter: 0.08ps (typ.), 156.25MHz (10kHz to 20MHz)
Excellent phase noise: -145dBc/Hz, 156.25MHz at 100kHz offset
Environmental Compliance Legend: LFF: Pb-Free Finish and RoHS 5/6 TLFP: Totally Pb-Free Product and RoHS 6/6 LFGP: Pb-free Finish and Green Product, RoHS 5/6 and Halogen Free TPGP: Totally Pb-Free and Green Product, RoHS 6/6 and Halogen Free GREEN: Halogen-free and RoHS compliant RoHS: RoHS compliant but NOT halogen-free
PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs. HiFlex Clock FInder tool
What is LVPECL clock and its termination?
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.