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The PI6LC48S04 is a 4-output clock synthesizer designed for serial reference clock applications. The device generates four copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz clock signal with 0.34ps phase jitter performance. The four outputs are organized in two banks of two LVDS and two low power HCSL ouputs.The device supports 3.3V and 2.5V voltage supplies and is packaged in a small 32-lead TQFN package.
Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output clock synthesized from a 25MHz fundamental mode crystal
Four differential clock outputs (two LVDS and two low power HCSL outputs)
Crystal interface designed for 25MHz, parallel resonant crystal
RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1MHz - 20MHz): 0.21ps (typical)
RMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz - 20MHz): 0.32ps (typical)
Power supply noise rejection PSNR: -50dB (typical)
LVCMOS interface levels for the frequency select input
PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs. HiFlex Clock FInder tool
What is LVPECL clock and its termination?
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.