CMOS & LVDS Ethernet Clock Generator
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The PI6LC4840 is an LC VCO based low phase noise design in- tended for the most demanding Ethernet applications. Common Ethernet frequencies of 25MHz and 125MHz are supported, with the 125Mhz having both LVDS and LVCMOS outputs for maximum flexibility. One 25Mhz LVCMOS non-PLL output is also available.
- 32-contact 5x5mm TQFN (ZH)
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Supply Voltage (V) | 3.3 |
| Additive Jitter (ps) | 0.45 |
| Skew (PS) | 0 |
| Maximum Output Frequency (MHz) | 1x 25 MHz, 3x 25/50 MHz, 3x 125 MHz, 3x 125MHz |
| Input Type(s) | Crystal |
| Output Type(s) | LVCMOS, LVDS |
| Number of Outputs | 10 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
| Supported Frequencies (MHz) | 125, 50, 25 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2520 | 2021-05-27 | 2021-08-27 | Qualified Additional Bump Site and Assembly/Test (A/T) Sites |
| PCN-2328 | 2018-04-12 | 2018-10-12 | Device End of Life for tray packaging only |
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
