NRND = Not Recommended for New Design
PCIe & Ethernet Clock Generator
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The PI6LC4830 is an LC VCO based low phase noise design intended for the most demanding PCIe® 2.0 applications. Use of the ultra-low noise LC VCO allows for much greater noise margins than traditional solutions. This is ideal for noisy environments.
Compliance (Only Automotive Supports PPAP) |
Standard |
|---|---|
Supply Voltage (V) |
3.3 |
Additive Jitter (ps) |
0.4 |
Skew (PS) |
0 |
Maximum Output Frequency (MHz) |
3x 100 MHz, 1x 100 MHz, 1x 50/100 MHz, 1x 25 MHz |
Input Type(s) |
Crystal, Differential |
Output Type(s) |
HCSL, LVCMOS, Differential |
Number of Outputs |
6 |
Supported Frequencies (MHz) |
100, 50, 25 |
Ambient or Junction Temperature (°C) |
-40 to 85 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
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A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2770 | 2025-10-30 | 2025-10-30 | Add Fab Site Code, Country of Diffusion (COD) and Assembly Site Origin (ASO) on Product and Shipping Labels for all Diodes Products |
| PCN-2698 | 2024-10-09 | 2025-04-09 | Product End of Life (EOL) |
| PCN-2520 | 2021-05-27 | 2021-08-27 | Qualified Additional Bump Site and Assembly/Test (A/T) Sites |
