PCIe & Ethernet Clock Generator
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The PI6LC4830 is an LC VCO based low phase noise design intended for the most demanding PCIe® 2.0 applications. Use of the ultra-low noise LC VCO allows for much greater noise margins than traditional solutions. This is ideal for noisy environments.
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Supply Voltage (V) | 3.3 |
| Additive Jitter (ps) | 0.4 |
| Skew (PS) | 0 |
| Maximum Output Frequency (MHz) | 3x 100 MHz, 1x 100 MHz, 1x 50/100 MHz, 1x 25 MHz |
| Input Type(s) | Crystal, Differential |
| Output Type(s) | HCSL, LVCMOS, Differential |
| Number of Outputs | 6 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
| Supported Frequencies (MHz) | 100, 50, 25 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2520 | 2021-05-27 | 2021-08-27 | Qualified Additional Bump Site and Assembly/Test (A/T) Sites |
| PCN-2328 | 2018-04-12 | 2018-10-12 | Device End of Life for tray packaging only |
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
