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The PI6CB33202 is a two-output very-low-power PCIe Gen1/ Gen2/Gen3/Gen4/Gen5 clock buffer. It takes a reference input to fan out two 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save eight external resistors and make layout easier. Individual OE pin for each output provides easier power management.
It uses Diodes proprietary PLL design to achieve very-low jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen5 requirements. Other than PCIe 100MHz support, this device also support Ethernet application with 50MHz, 125MHz, and 133.33MHz via SMBus. It provides various options such as different slew rate and amplitude through SMBUS, so users can configure the device easily to get the optimized performance for their individual boards.
3.3V Supply Voltage
HCSL Input: 100MHz; Also supports 50MHz, 125MHz, or 133.33MHz via SMBus
Two Differential Low-Power HCSL Outputs with On-Chip Termination
Default ZOUT = 85Ω
Spread Spectrum Tolerant
Individual Output Enable
Programmable Slew Rate and Output Amplitude for Each Output
Differential Outputs Blocked until PLL is Locked
Strapping Pins or SMBus for Configuration
Differential output-to-output skew <50ps
Very low jitter outputs
Differential cycle-to-cycle jitter <50ps - PCIe Gen1/Gen2/Gen3/Gen4/Gen5 CC compliant - PCIe Gen 2 and 3 SRiS and SRnS compliant
Environmental Compliance Legend: LFF: Pb-Free Finish and RoHS 5/6 TLFP: Totally Pb-Free Product and RoHS 6/6 LFGP: Pb-free Finish and Green Product, RoHS 5/6 and Halogen Free TPGP: Totally Pb-Free and Green Product, RoHS 6/6 and Halogen Free GREEN: Halogen-free and RoHS compliant RoHS: RoHS compliant but NOT halogen-free