Log in or register
to manage email notifications about changes to datasheets or PCNs for this part.
The PI6CB332001A is a 20-output, very low-power, PCIe® 1.0/2.0/3.0/4.0/5.0/6.0 clock buffer. The device is capable of distributing the reference clocks for UPI, SAS, SATA, and other applications. It takes a reference input to fanout twenty 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save 80 external resistors and make layout easier. OE pins combined with SMBus bits, as well as a 3-wire side band interface, provide easier power management for each output. All OE pins are power down tolerant, which allows the OE pins to be driven by external signals when the device is in a power down or reset condition. The device must reset and power up properly if these pins are driven to any valid voltage prior to the assertion of VDD or PWRGD#.
The device uses Diodes' proprietary design to achieve very low jitter that meets PCIe 1.0/2.0/3.0/4.0/5.0/6.0 requirements.
Supports Intel's DB2000QL spec
3V Supply Voltage
HCSL input: 100MHz (typ), up to 400MHz
20 Differential Low-power HCSL Outputs with On-chip Termination
Two Output Enable Control Modes
Traditional 8 OE# Pins with Power Down Tolerance and 20 SMBus bits
Simple 3-wire Side-Band Interface Real-time Control