NRND = Not Recommended for New Design
3.3V, 5+4 Output Zero-Delay Clock Driver with High Drive Outputs
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The PI6C2409-1H is a PLL based, zero-delay buffer, with the ability to distribute nine outputs of up to 133 MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL.
The PI6C2409-1H has two banks of four outputs that can be controlled by the selection inputs, SEL1 & SEL2. It also has a power sparing feature: when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all outputs are referenced from CLKIN. PI6C2409-1H is available in high drive and industrial environment versions.
An internal feedback on OUT0 is used to synchronize the outputs to the input; the relationship between loading of this signal and the outputs determines the input-output delay. PI6C2409-1H are characterized for both commercial and industrial operation
| Compliance (Only Automotive Supports PPAP) | Standard |
|---|---|
| Function | Zero-Delay Buffer |
| Number of Outputs | 9 |
| Output Type(s) | TTL |
| Maximum Output Frequency (MHz) | 133 |
| Additive Jitter (ps) | N/A |
| Supply Voltage (V) | 3.3 |
| Input Type(s) | TTL |
| Skew (ps) | 250 |
| Ambient or Junction Temperature (°C) | 0 to 70 °C |
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2642 | 2023-09-05 | 2024-03-05 | Device End of Life (EOL) |
