74HC138

Description

The 74HC138 is a high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enab°C will produce one active low output with the remaing seven being high. There are two active LOW enable inputs 1 and 2, and one active HIGH enable input E3. The disab°C device state results in all outputs being high. The enable state occurs with 1 and 2 asserted low and E3 asserted high. The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter.

Application(s)

Memory chip select decoding

Demultiplexing

Single line peripheral control

Allow simple serial bit streams from a microcontroller to control as many peripheral lines as needed