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74HC138

3-to-8 Line Decoder Demultiplexer

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Description

The 74HC138 is a high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enab°C will produce one active low output with the remaing seven being high. There are two active LOW enable inputs 1 and 2, and one active HIGH enable input E3. The disab°C device state results in all outputs being high. The enable state occurs with 1 and 2 asserted low and E3 asserted high. The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter.

Application(s)

Memory chip select decoding

Demultiplexing

Single line peripheral control

Allow simple serial bit streams from a microcontroller to control as many peripheral lines as needed

Product Specifications

Product Parameters

Number of Gates	-
Family	HC
V_{CC Min (V)}	2 V
V_CC Maximum Rating	6 V
tpd max @ (1.5V)	- ns
tpd max @ 1.8V (ns)	- ns
tpd max @ 2.5V (ns)	190 ns
tpd max @ 3.3V (ns)	- ns
tpd max @ 5.0V (ns)	38 ns
Input/ Output Current	4
Description	3-to-8 Line Decoder Demultiplexer
Output Type	Push-Pull

Technical Documents

Recommended Soldering Techniques

TN1.pdf

Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN #	Issue Date	Implementation Date	Subject
PCN-2512	2021-04-16	2021-07-16	Qualified Additional Assembly & Test (A/T) Site