Diodes Incorporated
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8-port, 16-lane PCIe 3.0 Packet Switch

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The DIODES PI7C9X3G816GP is a PCIe® GEN3 packet switch that supports 16 lanes of GEN3 SERDES in flexible 2-port, 3-port, 4-port, 5-port and 8-port configurations. The architecture of the PCIe packet switch allows the flexible port configuration by allocating variable lane widths for each port. The packet switch can be configured to have different port types such as upstream port, downstream ports and Cross-Domain End-Point (CDEP) ports to support various applications, which include port fan-out, dual-host connectivity. Inside the packet switch, multiple DMA channels are embedded to facilitate data communication more efficiently among host(s) and end-points.

In addition, the PI7C9X3G816GP offers some extra benefits such as “maintaining high signal integrity in stress channel”, “advanced power management mechanism”, “enhanced reliability, availability and serviceability (RAS)” and “Surprised Hot Plug with LED Enclosure Management”.


  • Port and Lane Configurations for 8-port/16-Lane PCI Express GEN3 packet switch
    • Configurable Upstream lane widths of x1, x2, x4 or x8
    • Configurable Downstream port number up to 7
    • Configurable Downstream lane widths of x1, x2, x4 or x8
  • Reference Clock Management
    • Integrated PCIe Gen3 clock buffer for all downstream ports
    • Support three reference clock structures (Common, SRNS and SRIS)
    • Handle SSC Isolation up to one port
    • Provide two clock application modes (Base and CDSR)
  • Power Management
    • Support 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)
    • Start-up power management scheme
      • “Empty” Hot-Plug ports put in P2 state
    • Support Message packet for System Power Management
      • Latency Tolerance Reporting (LTR)
      • Optimized Buffer Flush Fill (OBFF)
  • PHY and MAC Layers
    • PHY initial settings optionally programmable through JTAG, EEPROM, and SMBus/I2C
    • Adaptive Continuous Time Linear Equalizer and 5-tap Decision Feedback Equalizer for RX
    • Adaptive and programmable 3-tap TX equalization
    • RX Polarity Inversion and Lane Reversal (Refer to 5.1.4)
  • Data Link Layer
    • Programmable ACK latency timer to respond ACK based upon traffic condition
    • Configurable Flow Control Credit to balance bandwidth utilization and buffer usage
  • Transaction Layer
    • Packet forwarding options including Cut-Through and Store & Forward
    • Support up to 512-Byte Max Payload Size
    • Low packet forwarding latency < 150ns (typical case)
    • Access Control Service (ACS) for peer-to-peer traffic
    • Address Translation (AT) packet for SR-IOV application
    • Support Atomic operation
    • Support Multicast
    • Provide Performance Visibility for ingress/egress packet types and packet counts
  • Dual-Host Application
    • Support one Cross-Domain End-Point (CDEP) port for Host-to-Host Communications
    • Support Fail-over using CDEP port
    • Provide up to 4 physical or 8 virtual DMA channels enabling communications among Hosts and EPs
  • Reliability, Availability and Serviceability
    • Enhanced Advanced Error Reporting
    • End-to-End Data Protection with ECC
    • Error Handling Mechanism
    • Support Surprise Hot Removal
    • Support Downstream Port Containment (DPC)
    • Support Hot Plug for Upstream and Downstream port
    • Provide Serial and Parallel Hot Plug Types
    • Support LED Management
    • Thermal Sensor reporting operational temperature instantly
    • IEEE 1149.1 and 1149.6 JTAG interface support
  • Advanced Diagnostic Tools
    • PHY EyeTM
    • MAC ViewerTM (including embedded LA and LTSSM monitor)
    • On-the-fly PRBS loopback test
    • On-the-fly Compliance pattern test
  • Side-band Management Interface
  • Standard Compliance
    • Compliant with PCI Express Base Specification Revision 3.1
    • Compliant with PCI Express CEM Specification Revision 3.0
    • Compliant with Advanced Configuration Power Interface (ACPI) Specification
    • Compliant with System Management (SM) Bus, Version 2.0
  • Power & Package
    • Two power rails (0.95V and 1.8V)
    • Power consumption: 4.11W (full-loading at Tj=80℃)
    • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
    • Halogen and Antimony Free. “Green” Device (Note 3)
    • An automotive-compliant part is available under separate datasheet (The PI7C9X3G816GPQ)
  • Packages: 324-pin HFC 19mm x 19mm package

Product Specifications

Product Parameters

Ports 8
Lanes 16
Power 4.1 w
Latency 150 ns
Ambient or Junction Temperature (°C) -40 to 85
Compliance (Only Automotive supports PPAP) Standard

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Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN # Issue Date Implementation Date Subject
PCN-2558 2021-11-12 2022-05-12 Device End of Life (EOL)


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