Diodes Menu Close
Back to PCIe Switch

PI7C9X3G816GP

8-port, 16-lane PCIe 3.0 Packet Switch

Contact Sales

Log in or register to manage email notifications about changes to datasheets or PCNs for this part.

Description

The PI7C9X3G816GP is a PCIe® 3.0 packet switch that supports 16-lane SERDES in flexible 2-port, 3-port, 4-port, 5-port, and 8-port configurations. The architecture of the PCIe packet switch allows for flexible port configuration by allocating variable lane widths for each port. The packet switch can be configured to have different port types such as upstream ports, downstream ports, and Cross-Domain End-Point (CDEP) ports to support various applications, which include port fanout and dual-host connectivity.
Inside the packet switch, multiple DMA channels are embedded to facilitate data communication more efficiently among the host(s) and end points. The PI7C9X3G816GP offers additional benefits such as maintaining high-signal integrity in stress channels; advanced power management mechanisms; enhanced reliability, availability and serviceability (RAS); and surprised hot plug with LED enclosure management.

Feature(s)

  • Port and Lane Configurations for 8-port/16-Lane PCI Express 3.0 packet switch
    • Configurable Upstream lane widths of x1, x2, x4 or x8
    • Configurable Downstream port number up to 7
    • Configurable Downstream lane widths of x1, x2, x4 or x8
  • Reference Clock Management
    • Integrated PCIe 3.0 clock buffer for all downstream ports
    • Support three reference clock structures (Common, SRNS and SRIS)
    • Handle SSC Isolation up to one port
    • Provide two clock application modes (Base and CDSR)
  • Power Management
    • Support 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)
    • Start-up power management scheme
      • “Empty” Hot-Plug ports put in P2 state
    • Continuous power management scheme
      • Support ASPM L1 Sub-state (P1.1/P1.2)
    • Support Message packet for System Power Management
      • Latency Tolerance Reporting (LTR)
      • Optimized Buffer Flush Fill (OBFF)
  • PHY and MAC Layers
    • PHY initial settings optionally programmable through JTAG, EEPROM, and SMBus/I2C
    • Adaptive Continuous Time Linear Equalizer and 5-tap Decision Feedback Equalizer for RX
    • Adaptive and programmable 3-tap TX equalization
    • RX Polarity Inversion and Lane Reversal
  • Data Link Layer
    • Programmable ACK latency timer to respond ACK based upon traffic condition
    • Configurable Flow Control Credit to balance bandwidth utilization and buffer usage
  • Transaction Layer
    • Packet forwarding options including Cut-Through and Store & Forward
    • Support up to 512-Byte Max Payload Size
    • Low packet forwarding latency < 150ns (typical case)
    • Access Control Service (ACS) for peer-to-peer traffic
    • Address Translation (AT) packet for SR-IOV application
    • Support Atomic operation
    • Support Multicast
    • Provide Performance Visibility for ingress/egress packet types and packet counts
  • Dual-Host Application
    • Support one Cross-Domain End-Point (CDEP) port for Host-to-Host Communications
    • Support Fail-over using CDEP port
    • Provide up to 4 physical or 8 virtual DMA channels enabling communications among Hosts and EPs
  • Reliability, Availability and Serviceability
    • Enhanced Advanced Error Reporting
    • End-to-End Data Protection with ECC
    • Error Handling Mechanism
    • Support Surprise Hot Removal
    • Support Downstream Port Containment (DPC)
    • Support Hot Plug for Upstream and Downstream port
    • Provide Serial and Parallel Hot Plug Types
    • Support LED Management
    • Thermal Sensor reporting operational temperature instantly
    • IEEE 1 and 1149.6 JTAG interface support
  • Advanced Diagnostic Tools 
    • PHY EyeTM
    • MAC ViewerTM (including embedded LA)
    • PCIBUDDYTM
    • On-Line PRBS loopback test
    • On-Line Compliance pattern test

     

  • Side-band Management Interface
    • I2C/SMBUS/JTAG
    • SPI EEPROM
  • Standard Compliance
    • Compliant with PCI Express Base Specification Revision 1
    • Compliant with PCI Express CEM Specification Revision 0
    • Compliant with Advanced Configuration Power Interface (ACPI) Specification
    • Compliant with System Management (SM) Bus, Version 0
  • Power & Package
    • Two power rails (0.95V and 8V)
    • Power consumption: 4.11W (full-loading at Tj=80℃)
    • Totally Lead-Free & Fully RoHS Compliant

PCI Express®, PCIe®, PCI-SIG®, and PCI™ are trademarks or registered trademarks and/or service marks of PCI-SIG Corporation.

Product Specifications

Product Parameters

Ports 8
Lanes 16
Power 4.1 w
Latency 150 ns
Ambient or Junction Temperature (°C) -40 to 85
Compliance (Only Automotive supports PPAP) Standard

Related Content

Packages

Protocols

Technical Documents

Recommended Soldering Techniques

TN1.pdf

Additional Technical Documents are available upon request: 
Application information, Design tool model software, Design kits, Evaluation board, and Other technical documents

Request Documents
Orderable Part Number Status Package Environmental Compliance Packing Buy from Distributor /
Contact Sales
Request Samples
Qty. Carrier
PI7C9X3G816GPBHFCE Active H-FCBGA190190-324 LFGP 84 TRAY Contact Sales Request Sample

Environmental Compliance Legend:
LFF: Pb-Free Finish and RoHS 5/6
TLFP: Totally Pb-Free Product and RoHS 6/6
LFGP: Pb-free Finish and Green Product, RoHS 5/6 and Halogen Free
TPGP: Totally Pb-Free and Green Product, RoHS 6/6 and Halogen Free
GREEN: Halogen-free and RoHS compliant
RoHS: RoHS compliant but NOT halogen-free

PCNs

Product Change Notices

PCN # Issue Date Implementation Date Subject
PCN-2558 2021-11-12 2022-05-12 Device End of Life (EOL)

FAQs

Related Protocol FAQs