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The PI7C9X3G1632GP is a PCIe GEN3 packet switch that supports 32 lanes of GEN3 SERDES in flexible 2-port to 16-port configurations. The architecture of the PCIe packet switch allows the flexible port configuration by allocating variable lane width for each port. A basic cell of the switch architecture is called a tile, which consists of 8 ports and 16 lanes. The PI7C9X3G1632GP is built with 2 tiles connected by internal signal paths. Each tile can be configured to have different port types such as upstream port and downstream ports to support various port configurations for fan-out application in single switch or dual-switch partition modes. Besides fan-out, there are some designated ports can be programmed as Cross-Domain End-Point (CDEP) ports to allow multiple hosts connected to the switch for fail-over or multiple-host computation and communication applications. Inside the packet switch, multiple DMA channels are embedded to facilitate data communication more efficiently among hosts.
In addition, the PI7C9X3G1632GP offers some extra benefits such as “maintaining high signal integrity in stress channel”, “advanced power management mechanism”, “enhanced reliability, availability and serviceability (RAS)” and “Surprised Hot Plug with LED Enclosure Management”.