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PCIe3.0 12-Port/24-Lane Packet Switch

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The PI7C9X3G1224GP is a PCIe®GEN3 packet switch that supports 24 lanes of GEN3 SERDES in flexible 3-port to 12-port configurations. The architecture of the PCIe packet switch allows the flexible port configuration by allocating variable lane width for each port. A basic cell of the switch architecture is called a tile, which consists of 8 ports and 16 lanes for Tile 0, 4 ports and 8 lanes for Tile 1. The PI7C9X3G1224GP is built with 2 tiles connected by internal signal paths. Each tile can be configured to have different port types such as upstream port and downstream ports to support various port configurations for fan-out application in single switch or dual-switch partition modes. Besides fan-out, there are some designated ports can be programmed as Cross-Domain End-Point (CDEP) ports to allow multiple hosts connected to the switch for fail-over or multiple-host computation and communication applications. Inside the packet switch, multiple DMA channels are embedded to facilitate data communication more efficiently among hosts.

In addition, the PI7C9X3G1224GP offers some extra benefits such as “maintaining high signal integrity in stress channel”, “advanced power management mechanism”, “enhanced reliability, availability and serviceability (RAS)” and “Surprised Hot Plug with LED Enclosure Management”.


  • Port and Lane Configurations for 12-port/24-Lane PCI Express GEN3 packet switch
    • Configurable Upstream port number up to 2
    • Configurable Upstream lane widths of x1, x2, x4 or x8
    • Configurable Downstream port number up to 11
    • Configurable Downstream lane widths of x1, x2, x4 or x8
  • Reference Clock Management
    • Integrated PCIe Gen3 clock buffer for all downstream ports
    • Support three reference clock structures (Common, SRNS and SRIS)
    • Handle SSC Isolation up to three ports
    • Provide two clock application modes (Base and CDSR)
  • Power Management
    • Support 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)
    • Start-up power management scheme
      • “Empty” Hot-Plug ports put in P2 state
  • PHY and MAC Layers
    • PHY initial settings optionally programmable through JTAG, EEPROM, and SMBus/I2C
    • Adaptive Continuous Time Linear Equalizer and 5-tap Decision Feedback Equalizer for RX
    • Adaptive and programmable 3-tap TX equalization
    • RX Polarity Inversion and Lane Reversal
  • Data Link Layer
    • Programmable ACK latency timer to respond ACK based upon traffic condition
    • Configurable Flow Control Credit to balance bandwidth utilization and buffer usage
  • Transaction Layer
    • Packet forwarding options including Cut-Through and Store & Forward
    • Support up to 512-Byte Max Payload Size
    • Low packet forwarding latency < 150ns (typical case)
    • Access Control Service (ACS) for peer-to-peer traffic
    • Address Translation (AT) packet for SR-IOV application
    • Support Atomic operation
    • Support Multicast
    • Provide Performance Visibility for ingress/egress packet types and packet counts
  • Multi-Host Application
    • Support up to 3 Cross-Domain End-Point (CDEP) ports for Host-to-Host Communications
    • Support Fail-over using CDEP port
    • Provide up to 8 physical or 16 virtual DMA channels enabling communications among Hosts and EPs
    • Switch bifurcated up to 2 individual packet switches to allow 2 hosts operating independently
  • Reliability, Availability and Serviceability
    • Enhanced Advanced Error Reporting
    • End-to-End Data Protection with ECC
    • Error Handling Mechanism
    • Support Surprise Hot Removal
    • Support Downstream Port Containment (DPC)
    • Support Hot Plug for Upstream and Downstream port
    • Provide Serial and Parallel Hot Plug Types
    • Support LED Management
    • Thermal Sensor reporting operational temperature instantly
    • IEEE 1149.1 and 1149.6 JTAG interface support
  • Advanced Diagnostic Tools
    • PHY EyeTM
    • MAC ViewerTM (including embedded LA and LTSSM monitor)
    • On-the-fly PRBS loopback test
    • On-the-fly Compliance pattern test
  • Side-band Management Interface
  • Standard Compliance
    • Compliant with PCI Express Base Specification Revision 3.1
    • Compliant with PCI Express CEM Specification Revision 3.0
    • Compliant with Advanced Configuration Power Interface (ACPI) Specification
    • Compliant with System Management (SM) Bus, Version 2.0
  • Power & Package
    • Two power rails (0.95V and 1.8V)
    • Power consumption: 5.33W (Note 1)
    • Totally Lead-Free & Fully RoHS Compliant (Notes 2 & 3)
    • Halogen and Antimony Free. “Green” Device (Note 4)
    • For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/
    • Packages: 324 HFCBGA 19mm x 19mm
  • Operating Ambient Temperature
    • Support Industrial Temperature Range -40° to 85°C (Note 5)

Product Specifications

Product Parameters

Ports 12
Lanes 24
Power 5.3 w
Latency 150 ns
Ambient or Junction Temperature (°C) -40 to 85
Compliance (Only Automotive supports PPAP) Standard

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