PCIe Gen3 and Ethernet Clock Generator
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The PI6LC48H02 is a clock generator compliant to PCI Express® 3.0/2.0/1.0 and Ethernet requirements. The device is used for PC or embedded systems.
The PI6LC48H02 provides two differential (HCSL) or LVDS out- puts. Using Diodes' patented Phase Locked Loop (PLL) tech- niques, the device takes a 25MHz crystal input and produces two pairs of differential outputs (HCSL) at 25MHz, 100MHz, 125MHz, 200MHz clock frequencies.
- PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.)
- 16-pin TSSOP (L16)
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Supply Voltage (V) | 3.3 |
| Additive Jitter (ps) | 0.35 |
| Skew (PS) | 0 |
| Maximum Output Frequency (MHz) | 2x 25/ 100/ 125/ 200 MHz |
| Input Type(s) | Crystal, CMOS |
| Output Type(s) | HCSL |
| Number of Outputs | 2 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
| Supported Frequencies (MHz) | 25, 100, 125, 200 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
