HiFlex? High Performance Ethernet & Fibre Channel Clock Generator
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| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Supply Voltage (V) | 2.5, 3.3 |
| Additive Jitter (ps) | 0.25 |
| Skew (PS) | N/A |
| Maximum Output Frequency (MHz) | N/A |
| Input Type(s) | Crystal, CMOS, Differential |
| Output Type(s) | LVCMOS, LVPECL, LVDS |
| Number of Outputs | 6 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
| Supported Frequencies (MHz) | 156.25, 125, 106.25, 100, 33, 25 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2567 | 2022-03-30 | 2022-09-30 | Device End of Life (EOL) |
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
