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The PI6LC4840 is an LC VCO based low phase noise design in- tended for the most demanding Ethernet applications. Common Ethernet frequencies of 25MHz and 125MHz are supported, with the 125Mhz having both LVDS and LVCMOS outputs for maximum flexibility. One 25Mhz LVCMOS non-PLL output is also available.
3.3V supply voltage ± 5% Î Three banks of outputs:
- Bank A: 3 25/50MHz pin selectable LVCMOS outputs
- Bank B: 3 125MHz LVCMOS outputs
- Bank C: 3 125MHz LVDS outputs
1 25MHz LVCMOS reference clock output (no PLL)
25MHz crystal input (SaRonix-eCera P/N FL2500029)
Low 1ps max 12k-20MHz integrated phase noise design (for 125MHz CMOS and LVDS outputs)
Environmental Compliance Legend: LFF: Pb-Free Finish and RoHS 5/6 TLFP: Totally Pb-Free Product and RoHS 6/6 LFGP: Pb-free Finish and Green Product, RoHS 5/6 and Halogen Free TPGP: Totally Pb-Free and Green Product, RoHS 6/6 and Halogen Free GREEN: Halogen-free and RoHS compliant RoHS: RoHS compliant but NOT halogen-free
Product Change Notices (PCNs)
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs. HiFlex Clock FInder tool
What is LVPECL clock and its termination?
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.