Low Voltage LVCMOS Clock Buffer with Level Shift
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The PI6CL1001 is a low voltage, low- noise non-inverting LVCMOS single output clock buffer with level translation.
It supports 1.0V to 1.8V power supply. The key goal in designing the PI6CL1001 is to target networking applications that require low voltage power supply, low-jitter, and the capability to bridge the power supply mismatch between clock source and clock sink devices. VDD_IN supply voltage defines input clock level, and VDD_OUT supply voltage defines output clock level. The device is capable of translating clock levels from low to high or from high to low.
The device has a fail-safe input that prevents oscillation at the output in the absence of an input signal and allows for input signals before VDD is supplied.
Compliance (Only Automotive Supports PPAP) |
Standard |
|---|---|
Function |
CMOS Buffer with Level Shift |
Number of Outputs |
1 |
Output Type(s) |
LVCMOS |
Maximum Output Frequency (MHz) |
60 |
Additive Jitter (ps) |
0.2 |
Supply Voltage (V) |
1.0V-1.8V |
Input Type(s) |
LVCMOS |
Skew (ps) |
NA |
Ambient or Junction Temperature (°C) |
-40 to 105 °C |
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A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2770 | 2025-10-30 | 2025-10-30 | Add Fab Site Code, Country of Diffusion (COD) and Assembly Site Origin (ASO) on Product and Shipping Labels for all Diodes Products |