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The PI6CB33602 is a 6-output very low power PCIe Gen1/Gen2/ Gen3/Gen4/Gen5 clock buffer. It takes a reference input to fanout six 100MHz low power differential HCSL outputs with on-chip terminations. The on-chip termination can save 24 external resistors and make layout easier. Individual OE pin for each output provides easier power management.
It uses Diodes proprietary PLL design to achieve very low jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen5 requirements. Other than PCIe 100MHz support, this device also support Ethernet application with 50MHz, 125MHz and 133.33MHz via SMBus. It provides various options such as different slew rate and amplitude through SMBUS so that users can configure the device easily to get the optimized performance for their individual boards.
3.3V supply voltage
HCSL input: 100MHz, also support 50MHz, 125MHz or 133.33MHz via SMBus
6 differential low power HCSL outputs with on-chip termination
Default ZOUT = 85Ω
Spread spectrum tolerant
Individual output enable
Programmable Slew rate and output amplitude for each output