Diodes Incorporated
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1:4 Clock Driver for Intel PCIe® Chipsets

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Product Description

The  PI6C20400A is a PCIe® 2.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PI6C410BS. The device distributes the differential SRC clock from PI6C410BS to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is low, the output clocks are Tri-stated. When PWRDWN# is low, the SDA and SCLK inputs must be Tri-stated.


  • Phase jitter filter for PCIe® 2.0 application
  • Four Pairs of Differential Clocks
  • Low skew < 50ps
  • Low jitter < 50ps cycle-to-cycle
  • < 1 ps additive RMS phase jitter
  • Output Enable for all outputs
  • Outputs tristate control via SMBus
  • Programmable PLL Bandwidth
  • 100 MHz PLL Mode operation
  • 100 - 400 MHz Bypass Mode operation
  • 3.3V Operation
  • Packaging (Pb-free and Green):
    →28-Pin SSOP (H28)
    →28-Pin TSSOP (L28)

Product Specifications

Product Parameters

Compliance (Only Automotive(Q) supports PPAP) Standard
Function PCIe clock buffer
Number of Outputs 4
Output Type(s) HCSL
Maximum Output Frequency (MHz) 100
Additive Jitter (ps) 50
Supply Voltage (V) 3.3
Input Type(s) HCSL
Skew (PS) 50
Ambient or Junction Temperature (°C) -40 to 85

Technical Documents

Application Information

Evaluation Boards and User Guides

Design tool model software

Recommended Soldering Techniques


Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN # Issue Date Implementation Date Subject
PCN-2325 – Rev 3 (Interim Update) 2018-04-20 2020-11-20 Fab Porting from Global Foundries to MagnaChip