2.5Gbps 1.8V, 4 Lanes Data, 1 Lane Clock, MIPI ReDriver, CSI-2/DSI D-PHY
The PI2MEQX2505A is a low power, high performance 2.5Gbps four lanes data and clock MIPI D-PHY ReDriver™ designed specifically for MIPI D-PHY 1.2 protocol.
The device provides programmable equalization, output swing and pre-emphasis to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI2MEQX2505A supports MIPI D-PHY 1.2 standard with 100Ω differential CML data I/O between CSI-2 Source and CSI-2 Sink, over cable, or to extend the signals across other distant data pathways on the user’s platform. It also supports pin adjustable on receiver equalization and edge rate on transmitter rise and fall time.
PI2MEQX2505A is optimized for mobile applications, and contains activity detection circuitry on the D-PHY Link interface that can transit into a lower power mode when in ULPS and LP states.
Compliance (Only Automotive Supports PPAP) |
Standard |
|---|---|
Channels |
5,5 |
Data Rate (Gbps) |
2.5 |
Lanes/Ports |
1 |
Output Swing Max (mV) |
275 |
Programming Interface(s) |
I2C, Pin strap |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
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A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2770 | 2025-10-30 | 2025-10-30 | Add Fab Site Code, Country of Diffusion (COD) and Assembly Site Origin (ASO) on Product and Shipping Labels for all Diodes Products |