DMP2035UFCL

P-Channel Enhancement Mode MOSFET

Datasheet

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Description

This new generation MOSFET is designed to minimize the on-state resistance (R_DS(ON)), yet maintain superior switching performance, making it ideal for high-efficiency power management applications.

Feature(s)

Ideally Suited for Thin Applications
Low R_DS(ON) - Minimizes Conduction Losses
PCB Footprint of 2.56mm²
ESD Protected Gate

Application(s)

Power Management Functions
Analog Switches
STB
LCD-TV
Motherboard
Notebooks
Monitors
Access Point
Gateways
Cable Modems
VOIP
xDSL Modems

Specifications & Technical Documents

Product Parameters

Compliance (Only Automotive Supports PPAP)	Standard
AEC Qualified	Yes
Polarity	P
ESD Diodes (Y\|N)	Yes
\|V_DS\| (V)	20 V
\|V_GS\| (±V)	8 ±V
\|I_DS\| @T_A = +25°C (A)	6.6 A
P_D @T_A = +25°C (W)	1.6 W
R_DS(ON)Max@ V_GS(4.5V) (mΩ)	24 mΩ
R_DS(ON)Max@ V_GS(2.5V) (mΩ)	31 mΩ
R_DS(ON)Max@ V_GS(1.8V) (mΩ)	45 mΩ
\|V_GS(TH)\| Min (V)	0.4 V
\|V_GS(TH)\| Max (V)	1 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	15.4 nC
Q_G Typ @ \|V_GS\| = 10V (nC)	29 (@8V) nC
C_ISS Typ (pF)	1610 pF
C_ISS Condition @\|V_DS\| (V)	10 V

Technical Documents

SPICE Model

DMP2035UFCL.spice.txt

Recommended Soldering Techniques

TN1.pdf

Purchase & Availability

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