DMP1010UCA4

P-Channel Enhancement Mode MOSFET

Datasheet

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Description

This new generation Lateral MOSFET (LD-MOS) is designed to minimize on-state losses and switch ultra-fast, making it ideal for high-efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal R_DS(ON)per footprint area.

Feature(s)

LD-MOS Technology with the Lowest Figure of Merit:
- R_DS(ON)= 9.9mΩ to Minimize On-State Losses
- Q_g = 7.0nC for Ultra-Fast Switching
V_GS(TH)= -0.80V typ. for a Low Turn-On Potential
CSP with Footprint 1.2mm x 1.2mm
Height = 0.35mm for Low Profile
ESD Protected Gate
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/

Application(s)

Battery protections
Battery managements
Load switches

Specifications & Technical Documents

Product Parameters

Compliance (Only Automotive Supports PPAP)	Standard
AEC Qualified	No
Polarity	P
ESD Diodes (Y\|N)	Yes
\|V_DS\| (V)	8 V
\|V_GS\| (±V)	6 ±V
\|I_DS\| @T_A = +25°C (A)	10 A
P_D @T_A = +25°C (W)	1.75 W
R_DS(ON)Max@ V_GS(4.5V) (mΩ)	9.9 mΩ
R_DS(ON)Max@ V_GS(2.5V) (mΩ)	15 mΩ
R_DS(ON)Max@ V_GS(1.8V) (mΩ)	40 mΩ
\|V_GS(TH)\| Min (V)	0.4 V
\|V_GS(TH)\| Max (V)	1.05 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	7 nC
C_ISS Typ (pF)	699 pF
C_ISS Condition @\|V_DS\| (V)	4 V

Technical Documents

SPICE Model

DMP1010UCA4.spice.txt

Recommended Soldering Techniques

TN1.pdf

Purchase & Availability

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