Diodes Incorporated
U WLB1515 9

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DMP1008UCB9

P-CHANNEL ENHANCEMENT MODE MOSFET

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Description

This 3rd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(ON) per footprint area.

Feature(s)

  • LD-MOS Technology with the Lowest Figure of Merit:
  • RDS(ON) = 5.7mΩ to Minimize On-State Losses
  • Qg = 8.2nC for Ultra-Fast Switching
  • VGS(TH) = -0.6V Typ. for a Low Turn-On Potential
  • CSP with Footprint 1.5mm  1.5mm
  • Height = 0.60mm for Low Profile
  • ESD Protection of Gate
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
  • Halogen and Antimony Free. “Green” Device (Note 3)
  • For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/

Application(s)

  • DC-DC Converters
  • Battery Management
  • Load Switch

Product Specifications

Product Parameters

AEC Qualified No
Compliance (Only Automotive(Q) supports PPAP) Standard
Polarity P
ESD Diodes (Y|N) Yes
|VDS| (V) 8 V
|VGS| (±V) 6 ±V
|IDS| @TA = +25°C (A) 13.2 A
PD @TA = +25°C (W) 1.53 W
RDS(ON)Max@ VGS(4.5V)(mΩ) 5.7 mΩ
RDS(ON)Max@ VGS(2.5V)(mΩ) 9.1 mΩ
|VGS(TH)| Min (V) 0.4 V
|VGS(TH)| Max (V) 1.1 V
QG Typ @ |VGS| = 4.5V (nC) 8.2 nC
CISS Typ (pF) 900 pF
CISS Condition @|VDS| (V) 4 V

Related Content

Packages

Applications

Technical Documents

SPICE Model

Recommended Soldering Techniques

TN1.pdf

RoHS CofC

FAQs

Related Application FAQs