DMP1008UCA9

P-Channel Enhancement Mode MOSFET

Datasheet

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Description

This 3rd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(ON) per footprint area.

Feature(s)

LD-MOS Technology with the Lowest Figure of Merit:

RDS(ON) = 5.7mΩ to Minimize On-State Losses
Qg = 9.5nC for Ultra-Fast Switching

VGS(TH) = -0.7V Typ. for a Low Turn-On Potential
CSP with Footprint 1.5mm x 1.5mm
Height = 0.34mm for Low Profile
ESD Protection of Gate

Application(s)

DC-DC Converters
Battery Management
Load Switch

Specifications & Technical Documents

Product Parameters

Compliance (Only Automotive Supports PPAP)	Standard
AEC Qualified	No
Polarity	P
ESD Diodes (Y\|N)	Yes
\|V_DS\| (V)	8 V
\|V_GS\| (±V)	6 ±V
\|I_DS\| @T_A = +25°C (A)	16 A
P_D @T_A = +25°C (W)	2.2 W
R_DS(ON)Max@ V_GS(4.5V) (mΩ)	5.7 mΩ
R_DS(ON)Max@ V_GS(2.5V) (mΩ)	9.1 mΩ
\|V_GS(TH)\| Min (V)	0.4 V
\|V_GS(TH)\| Max (V)	1.1 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	9.5 nC
C_ISS Typ (pF)	952 pF
C_ISS Condition @\|V_DS\| (V)	4 V

Technical Documents

SPICE Model

DMP1008UCA9 .spice.txt

Recommended Soldering Techniques

TN1.pdf

RoHS CofC

RoHSFile

Purchase & Availability

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