DMN1054UCB4

N-Channel Enhancement Mode MOSFET

Datasheet

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Description

This 3rd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(on) per footprint area.

Feature(s)

 LD-MOS Technology with the Lowest Figure of Merit:
RDS(on) = 37mΩ to Minimize On-State Losses
Qg = 7.5nC for Ultra-Fast Switching
Vgs(th) = 0.6V typ. for a Low Turn-On Potential
CSP with Footprint 0.8mm × 0.8mm
Height = 0.35mm for Low Profile

Application(s)

DC-DC Converters
Battery Management
Load Switch

Specifications & Technical Documents

Product Parameters

Compliance (Only Automotive Supports PPAP)	Standard
AEC Qualified	No
Polarity	N
ESD Diodes (Y\|N)	No
\|V_DS\| (V)	8 V
\|V_GS\| (±V)	5 ±V
\|I_DS\| @T_A = +25°C (A)	4 A
P_D @T_A = +25°C (W)	1.34 W
R_DS(ON)Max@ V_GS(4.5V) (mΩ)	42 mΩ
R_DS(ON)Max@ V_GS(2.5V) (mΩ)	50 mΩ
R_DS(ON)Max@ V_GS(1.8V) (mΩ)	65 mΩ
\|V_GS(TH)\| Max (V)	0.7 V
Q_G Typ @ \|V_GS\| = 4.5V (nC)	9.6 nC
C_ISS Typ (pF)	590 pF
C_ISS Condition @\|V_DS\| (V)	6 V

Technical Documents

SPICE Model

DMN1054UCB4.spice.txt

Recommended Soldering Techniques

TN1.pdf

Purchase & Availability

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