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DMN1032UCP4

N-Channel Enhancement Mode MOSFET

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Description

This 2nd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(ON) per footprint area.

Feature(s)

  • LD-MOS Technology with the Lowest Figure of Merit:
    • RDS(ON) = 18mΩ to Minimize On-State Losses
    • Qg = 3.2nC for Ultra-Fast Switching
  • VGS(th) = 8V Typ. for a Low Turn-On Potential
  • CSP with Footprint 1.0mm × 1.0mm
  • Height = 0.45mm for Low Profile
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
  • Halogen and Antimony Free. “Green” Device (Note 3)
  • For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative.

https://www.diodes.com/quality/product-definitions/

Application(s)

  • DC-DC converters
  • Battery management
  • Load switches

Specifications & Technical Documents

Product Parameters

Compliance (Only Automotive Supports PPAP)

Standard

AEC Qualified

No

Polarity

N

ESD Diodes (Y|N)

No

|VDS| (V)

12 V

|VGS| (±V)

8 ±V

|IDS| @TA = +25°C (A)

5 A

PD @TA = +25°C (W)

1.01 W

RDS(ON)Max@ VGS(4.5V)  (mΩ)

28 mΩ

RDS(ON)Max@ VGS(2.5V)  (mΩ)

32 mΩ

RDS(ON)Max@ VGS(1.8V)  (mΩ)

42 mΩ

|VGS(TH)| Min (V)

0.4 V

|VGS(TH)| Max (V)

1.2 V

QG Typ @ |VGS| = 4.5V (nC)

3.2 nC

CISS Typ (pF)

325 pF

CISS Condition @|VDS| (V)

6 V

Technical Documents

SPICE Model

Recommended Soldering Techniques

TN1.pdf

Purchase & Availability

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