Diodes Incorporated
Back to Standard Logic


Octal Transparent D-Type Latch with 3-State Outputs

Contact Sales

Log in or register to manage email notifications about changes to datasheets or PCNs for this part.


The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. The device is designed for operation with a power supply range of 1.65V to 3.6V.

The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.


  • Supply Voltage Range from 1.65V to 3.6V 
  • Sinks or Sources 24mA at VCC = 3V 
  • CMOS Low Power Consumption 
  • IOFF Supports Partial-Power Down Operation 
  • Inputs or Outputs Accept Up to 5.5V 
  • Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications 
  • Schmitt Trigger Action at All Inputs 
  • Typical VOLP (Quiet Output Ground Bounce) less than 0.8V with VCC = 3.3V and TA = +25°C 
  • Typical VOHV (Quiet Output Dynamic VOH) greater than 2.0V with VCC = 3.3V and TA = +25°C 
  • ESD Protection Tested per JESD 22
    • Exceeds 200-V Machine Model (A115) 
    • Exceeds 2000-V Human Body Model (A114) 
    • Exceeds 1000-V Charged Device Model (C101) 
  • Latch-Up Exceeds 250mA per JESD 78, Class I 
  • All devices are:
    • Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2) 
    • Halogen and Antimony Free. “Green” Device (Note 3) 


  • General Purpose Logic
  • Bus Driving
  • Power Down Signal Isolation
  • Wide Array of Products Such as:
    • PCs, Notebooks, Netbooks, Ultrabooks
    • Networking Computer Peripherals, Hard Drives, CD/DVD ROM
    • TV, DVD, DVR, Set Top Box

Product Specifications

Product Parameters

Number of Gates 8
Family LVC
VCC Min (V) 1.65 V
VCC Maximum Rating 3.6 V
tpd max @ (1.5V) - ns
tpd max @ 1.8V (ns) 12.7 ns
tpd max @ 2.5V (ns) 8.3 ns
tpd max @ 3.3V (ns) 6.3 ns
tpd max @ 5.0V (ns) - ns
Input/ Output Current 24
Description Octal Transparent D-Type Latch with 3-State Outputs
Output Type 3-State

Related Content


Technical Documents

Recommended Soldering Techniques