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The 74LVC374A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The ‘374A is functionally identical to the ‘574A, but the ’574 has a different pin arrangement.
The device is designed for operation with a power supply range of 1.65V to 3.6V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF.
Supply Voltage Range from 1.65V to 3.6V
Sinks or Sources 24ma at VCC = 3V
CMOS Low Power Consumption
IOFF Supports Partial Power Down Operation
Inputs or Outputs Accept Up to 5.5V
Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications
Schmitt Trigger Action at All Inputs
Typical VOLP (Quiet Output Ground Bounce) Less Than 0.8V with VCC = 3.3V and TA = +25°C
Typical VOHV (Quiet Output dynamic VOH) Greater than 2.0V with VCC = 3.3V and TA = +25°C