Diodes Incorporated
X2 DFN0808 4

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X2-DFN0808-4.png
X2 DFN1010 6

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X2 DFN1410 6

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74AUP1G34

Single Buffer

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Description

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G34 is a single buffer gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.

Feature(s)

  • Advanced Ultra Low Power (AUP) CMOS
  • Supply Voltage Range from 0.8V to 3.6V
  • ±4mA Output Drive at 3.0V
  • Low Static power consumption
  • Application(s)

  • Suited for battery and low power needs
  • Wide array of products such as:
  • Product Specifications

    Product Parameters

    Function Buffer
    Type Buffers/Inverters/Transceivers
    Compliance (Only Automotive supports PPAP) Standard
    Channels 1
    Family AUP
    VCC Min (V) 0.8
    VCC Max (V) 3.6
    Input Type Standard CMOS
    Output Type Push-Pull
    Output Current (mA) 4

    Technical Documents

    Recommended Soldering Techniques

    TN1.pdf

    Product Change Notices (PCNs)

    A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

    PCN # Issue Date Implementation Date Subject
    PCN-2299 2018-03-01 2018-06-01 Additional Qualified (A/T) Assembly Test Site