Diodes Incorporated
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PI6LC48H02Q

PCIe 3.0 and Ethernet Clock Generator

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Description

The PI6LC48H02Q is a clock generator compliant to PCI Express® 3.0/2.0/1.0 and Ethernet requirements. The device is designed for automotive applications. The PI6LC48H02Q provides two differential (HCSL) or LVDS outputs. Using Pericom's patented Phase Locked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces two pairs of differential outputs (HCSL) at 25MHz, 100MHz, 125MHz, 200MHz clock frequencies.

Features

  • PCIe® 3.0/2.0/1.0 compliant
    - PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.)
  • LVDS compatible outputs
  • Supply voltage of 3.3V ±10%
  • 25MHz crystal or clock input frequency
  • HCSL outputs, 0.8V Current mode differential pair
  • Jitter 35ps cycle-to-cycle (typ)
  • RMS phase jitter 12kHz ~ 20MHz @ 100MHz - 0.32ps (typ)
  • RMS phase jitter 12kHz ~ 20MHz @ 125MHz - 0.3ps (typ)
  • Automotive Grade 3 temperature range
  • Packaging: (Pb-free and Green
    - 16-pin TSSOP (L16)

Product Specifications

Product Parameters

AEC Qualified Yes
Compliance (Only Automotive supports PPAP) Automotive
Input Type(s) Crystal, LVCMOS
Maximum Output Frequency (MHz) 100
Output Type(s) HCSL
Additive Jitter (ps) 0.45
Number of Outputs 2
Skew (PS) 50
Supply Voltage (V) 3.3
Ambient or Junction Temperature (°C) -40 to 85

Related Content

Packages

Technical Documents

Recommended Soldering Techniques

TN1.pdf

FAQs

PI6LC48H02Q FAQs

What is LVPECL clock and its termination?

LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet  to prevent double termination.