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The PI6LC4833 implements Diodes' advanced LC VCO tech- nology and is specifically designed for Power PC network pro- cessor (Freescale MPC8548, MPC8572, AMCC 460, AMI732). This high performance device is optimized to generate CPU core/ PCI clock, high performance PCIe Gen1/2 Clock, SRIO, Gigabit Ethernet’s MAC and PHY clock. All outputs are generated from 25MHz external clock input or crystal.
2.5/3.3V supply voltage
4 HCSL 100/125/200/250MHz outputs with OE
2 LVCMOS 33/50/66/100MHz selectable outputs
5 LVCMOS 25MHz or 125MHz outputs
1 LVPECL 312.5MHz, 156.25MHz or 125MHz output
1 CMOS 156.25MHz or 125MHz output
1 LVPECL 125MHz or 25MHz output
25MHz crystal or differential input
0.5ps (typ) RMS integrated phase noise design at 3.3V operation
1.0ps (typ) RMS integrated phase noise design at 2.5V operation
Environmental Compliance Legend: LFF: Pb-Free Finish and RoHS 5/6 TLFP: Totally Pb-Free Product and RoHS 6/6 LFGP: Pb-free Finish and Green Product, RoHS 5/6 and Halogen Free TPGP: Totally Pb-Free and Green Product, RoHS 6/6 and Halogen Free GREEN: Halogen-free and RoHS compliant RoHS: RoHS compliant but NOT halogen-free
Product Change Notices (PCNs)
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs. HiFlex Clock FInder tool
What is LVPECL clock and its termination?
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.