Clock Generator for Power PC
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The PI6LC4833 implements Diodes' advanced LC VCO tech- nology and is specifically designed for Power PC network pro- cessor (Freescale MPC8548, MPC8572, AMCC 460, AMI732). This high performance device is optimized to generate CPU core/ PCI clock, high performance PCIe Gen1/2 Clock, SRIO, Gigabit Ethernet’s MAC and PHY clock. All outputs are generated from 25MHz external clock input or crystal.
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Supply Voltage (V) | 2.5, 3.3 |
| Additive Jitter (ps) | 0.5 |
| Skew (PS) | 0 |
| Maximum Output Frequency (MHz) | 4x 100/125/ 200/250 MHz, 2x 33/50/66/100 MHz, 5x 25/125 MHz, 1x 312.5/156.25/125 MHz, 1x 156.25/125 MHz, 1x 125/25 MHz |
| Input Type(s) | Crystal, Differential |
| Output Type(s) | HCSL, LVCMOS, LVPECL, CMOS |
| Number of Outputs | 14 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
| Supported Frequencies (MHz) | 312.5, 250, 200, 156.25, 125, 100, 66, 50, 33 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2567 | 2022-03-30 | 2022-09-30 | Device End of Life (EOL) |
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
