4-Output Low Power PCIE GEN 1-2-3 Buffer
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PI6CDBL402B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator. It is backward compatible with PCIe 1.0 and 2.0 specification.
The device distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of PWRDWN# and SMBus, SCLK and SDA.
Compliance (Only Automotive Supports PPAP) |
Standard |
|---|---|
Function |
PCIe clock buffer |
Number of Outputs |
4 |
Output Type(s) |
HCSL |
Maximum Output Frequency (MHz) |
100 |
Additive Jitter (ps) |
50 |
Supply Voltage (V) |
3.3 |
Input Type(s) |
HCSL |
Skew (PS) |
50 |
Ambient or Junction Temperature (°C) |
-40 to 85 |
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A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2770 | 2025-10-30 | 2025-10-30 | Add Fab Site Code, Country of Diffusion (COD) and Assembly Site Origin (ASO) on Product and Shipping Labels for all Diodes Products |
