Diodes Incorporated
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4-Output Low Power PCIE GEN 1-2-3 Buffer

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Product Description

PI6CDBL402B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator. It is backward compatible with PCIe 1.0 and 2.0 specification.
The device distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without PLL.  The clock outputs are controlled by input selection of PWRDWN# and SMBus, SCLK and SDA. 


  • Phase jitter filter for PCIe 3.0/ 2.0/ 1.0 application
  • Low power consumption with independent output power supply 1.8V~3.3V
  • Low skew < 60ps
  • Low cycle-to-cycle jitter - 45ps (typ.) @100MHz
  • < 1 ps additive RMS phase jitter
  • Output Enable for all outputs
  • Programmable PLL Bandwidth
  • 100 MHz PLL Mode operation
  • 1 - 400 MHz Bypass Mode operation
  • 3.3V Operation
  • Packaging (Pb-free and Green):
       -28-Pin TSSOP (L28) 

Product Specifications

Product Parameters

Compliance (Only Automotive(Q) supports PPAP) Standard
Function PCIe clock buffer
Number of Outputs 4
Output Type(s) HCSL
Maximum Output Frequency (MHz) 100
Additive Jitter (ps) 50
Supply Voltage (V) 3.3
Input Type(s) HCSL
Skew (PS) 50
Ambient or Junction Temperature (°C) -40 to 85