PI6C4911504D2

LVPECL Clock Buffer with "divide by 2" feature

Datasheet

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Product Description

PI6C4911504D2 is a high performance differential buffer with divide by 2 capability. There are also 2 selectable muxed inputs. This device is ideal for systems that need to distribute low jitter clock signals to multiple destinations with a change from the input frequency.

Features

2 pairs of selectable differential inputs
2 divide by 2 differential LVPECL outputs and 2 buffered outputs
Maximum operating frequency: 650MHz
RMS additive jitter @ 156.25MHz (12kHz – 20MHz): 30fs (typical)
Output skew: 60ps
Part to part skew: 200ps
Operating voltage of 2.5V and 3.3V
Industrial operating temperature
Available in lead-free package

Applications

Networking: 10GbE, 25GbE, 40GbE and 100GbE applications
Telecom: Basestations and Access Points

Product Specifications

Product Parameters

Compliance (Only Automotive(Q) supports PPAP)	Standard
Function	Buffer
Number of Outputs	4
Output Type(s)	LVPECL
Maximum Output Frequency (MHz)	650
Additive Jitter (ps)	0.03
Supply Voltage (V)	2.5, 3.3
Input Type(s)	LVCMOS, Differential
Skew (ps)	65
Ambient or Junction Temperature (°C)	-40 to 85