Navigating the PCIe 6.0 Era: Boosting Performance with ReDrivers™

By John Bai, HPI BU Marketing Director

The digital world is evolving at an unprecedented pace, driven by the insatiable demand for faster data processing, higher computational efficiency, and scalable architectures, especially in areas like AI and high-performance computing (HPC). At the core of this transformation lies the PCI Express® (PCIe®) standard, which has been the de facto interconnect of choice for nearly three decades, providing the high bandwidth and low latency that system designers demand. The latest evolution, the PCIe 6.0 specification, is set to redefine performance boundaries, but it also brings new design challenges.

The Promise of PCIe 6.0

PCIe 6.0 represents a significant leap forward from its predecessor, PCIe 5.0. The technology integrates industry-leading feature enhancements, such as PAM4 (pulse amplitude modulation with 4 levels) signaling and flit (flow control unit) based encoding to deliver a 64GT/s (Gigatransfers per second) PAM4 data rate, a 100% increase from the 32GT/s delivered by PCIe 5.0. This is coupled with low-latency forward error correction (FEC) to improve bandwidth efficiency while maintaining the minimal complexity expected from the PCIe standard.

As emerging markets and advanced applications grapple with complex infrastructures involving CPUs, AI accelerators (GPUs), storage devices, and networks, PCIe 6.0 technology serves as a high-bandwidth, low-latency connection, enabling enhanced performance. Its scalability to hundreds of lanes at a low cost makes it ideal for data-intensive markets such as AI data centers (storage and servers), workstations, 5G networking, and HPC clusters.

A crucial advantage is its maintenance of compatibility with all previous generations of PCIe technology. This protects existing investments and offers developers the flexibility to innovate while preserving connections to millions of existing products.

The Signal Integrity Hurdles of PCIe 6.0

While PCIe 6.0 offers impressive performance gains, it introduces significant signal integrity (SI) challenges for developers. As signaling frequencies increase, so do losses across PCB traces, connectors, vias, and cables.

Unlike the nonreturn-to-zero (NRZ) signaling used by PCIe 5.0, PCIe 6.0’s PAM4 encodes two bits per unit interval, resulting in four voltage levels and three ‘eyes’ instead of one. Since the overall voltage swing remains fixed, each eye in the PAM4 system offers only one-third of the voltage available in NRZ, making the signal far more susceptible to noise and leading to a signal-to-noise ratio (SNR) degradation of 9.5dB^[1].

The complex signaling and higher data rates result in increased jitter, degrading signal quality, and leading to errors. The design requirement is to ensure reference clock RMS jitter does not exceed 0.25psRMS in PCIe 5.0^[2], this has been trimmed by a third to 0.15psRMS in PCIe 6.0. The channel loss budget for PCIe 6.0 is a tighter 32dB, compared to 36dB for PCIe 5.0, demanding precise signal loss management in system designs^[3].

Limited rise time and transition amplitudes in PCIe 6.0 necessitate complex equalization and clock recovery mechanisms. Furthermore, shrinking process geometries in SoCs can lead to reduced drive signals and output, potentially making communication channels unreliable. High drive output from integrated solutions can also generate EMI, disrupting nearby circuitry.

Understanding Signal Conditioning: Retimers vs. ReDrivers

To overcome these challenges, signal conditioning devices are essential to restore signal integrity using emphasis and equalization techniques. Two primary solutions exist: the Retimer and the ReDriver^[4].

Retimers improve signal quality and extend signal distance by terminating the incoming signal and then re-transmitting a new, clean signal. They are well-suited for very long, open-channel interfaces.

In contrast, ReDrivers are placed in-line within the communication channel to receive the signal, adjust for losses that have already occurred, and compensate for losses that will occur along the rest of the channel.

A key advantage of ReDrivers is their protocol independence, meaning they can pass link training signals through without disruption. They achieve this through a linear amplifier that preserves the input waveform, preventing clipping issues that can occur with limiting amplifiers and ensuring all link training signals are passed correctly, allowing signals to travel reliably over longer distances and through additional connectors.

Compared to Retimers, ReDrivers offer significant advantages for typical channel lengths: lower power consumption, less latency, no need for an external clock, a smaller footprint with minimal external components, and a lower overall system cost. They are a cost-effective solution for most channels, particularly medium-length closed channels.

PI3EQX64904 ReDriver for PCIe 6.0

The PI3EQX64904 ReDriver from Diodes Incorporated (Diodes) is engineered to tackle the significant signal integrity challenges presented by the PCIe 6.0 standard.

As mentioned previously, one primary challenge is the increased losses across PCB traces, connectors, vias, and cables as signaling frequencies rise. The PI3EQX64904 addresses this through its optimized linear equalization, which features tunable low-frequency and high-frequency zeroes at its equalizer stage. This design improves output linearity and minimizes return losses. Furthermore, its equalization, which can be controlled via I2C or Pin-Strap, optimizes performance over a variety of physical media by reducing intersymbol interference. This capability enables it to extend PCB trace lengths and ensures optimized performance across a wide range of PCB trace lengths, directly mitigating the impact of signal degradation over physical channels. Furthermore, the PI3EQX64904 allows for precise tuning across a range of +0.4 to +10.6dB to compensate for limited rise time and transition amplitudes characteristics.

Another significant hurdle is PCIe 6.0’s adoption of PAM4 encoding, leading to a 9.5dB SNR degradation compared to NRZ signaling. The PI3EQX64904 is specifically designed as a 64GT/s PAM4, 4-channel linear ReDriver that is compliant with PCIe 6.0, SAS4, and CXL protocols, making it inherently suited to manage the complexities and reduced eye height of PAM4 signals. Its sophisticated linear equalization further supports the integrity of these multi-level signals.

The standard also introduces increased jitter, demanding a significantly tighter reference clock RMS jitter not exceeding 0.15psRMS for PCIe 6.0. The PI3EQX64904 directly counters this by delivering elevated linearity and ultra-low jitter characteristics, ensuring robust signal quality despite these stringent demands.

PCIe 6.0 also imposes a tighter channel loss budget of 32dB, necessitating precise signal loss management. The PI3EQX64904 achieves a differential return loss of less than -15dB and common-mode return loss of less than -8dB at 16GHz, which is critical for meeting the strict channel loss requirements.

Beyond directly addressing signal integrity, the PI3EQX64904 also supports Modern Standby mode requirements and features less than 5mW power consumption when the system is in PCIe L1.2 deep standby mode. This power efficiency contributes to overall system design flexibility, especially important for applications like AI infrastructure. The device is available in a tiny WLGA-31L package. This compact design means it occupies only 6.1mm x 2.7mm on the PCB.

Conclusion

As the industry transitions to PCIe 6.0, addressing advanced signal integrity issues becomes paramount. While Retimers serve a purpose in extending reach, Diodes' PI3EQX64904 ReDriver emerges as a highly beneficial solution. Its ability to deliver enhanced signal quality through optimized linear equalization, coupled with its low power consumption, compact form factor, and transparent operation, makes it an ideal choice for ensuring robust and reliable high-speed communications.

 
[1] https://pcisig.com/blog/pci-express%C2%AE-50-architecture-channel-insertion-loss-budget
[2] https://pcisig.com/blog/seamless-transition-pcie%C2%AE-50-technology-system-implementations-webinar-qa
[3] https://www.opencompute.org/documents/ocp-pcie-extended-connectivity-requirements-v0-7a-docx-pdf
[4] https://www.diodes.com/assets/whitepapers/Overcoming_Advanced_Signal_Integrity_Issues.pdf

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