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The PI7C9X3G808GP is a PCIe GEN3 packet switch that supports 8 lanes of GEN3 SERDES in flexible 2-port, 3-port, 4-port, 5-port and 8-port configurations. The architecture of the PCIe packet switch allows the flexible port configuration by allocating variable lane widths for each port. The packet switch can be configured to have different port types such as upstream port, downstream ports and Cross-Domain End-Point (CDEP) ports to support various applications, which include port fan-out, dual-host connectivity. Inside the packet switch, multiple DMA channels are embedded to facilitate data communication more efficiently among host(s) and end-points.
Port and Lane Configurations for 8-port/8-Lane PCI Express GEN3 packet switch 。 Configurable Upstream lane widths of x1, x2 or x4 。 Configurable Downstream port number up to 7 。 Configurable Downstream lane widths of x1, x2 or x4
Reference Clock Management 。 Integrated PCIe Gen3 clock buffer for all downstream ports 。 Support three reference clock structures (Common, SRNS and SRIS) 。 Handle SSC Isolation up to one port 。 Provide two clock application modes (Base and CDSR)
Power Management 。 Support 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG) 。 Start-up power management scheme - “Empty” Hot-Plug ports put in P2 state 。 Continuous power management scheme - Support ASPM L1 Sub-state (P1.1/P1.2) 。 Support Message packet for System Power Management - Latency Tolerance Reporting (LTR) - Optimized Buffer Flush Fill (OBFF)
PHY and MAC Layers 。 PHY initial settings optionally programmable through JTAG, EEPROM, and SMBus/I2C 。 Adaptive Continuous Time Linear Equalizer and 5-tap Decision Feedback Equalizer for RX 。 Adaptive and programmable 3-tap TX equalization 。 RX Polarity Inversion and Lane Reversal
Data Link Layer 。 Programmable ACK latency timer to respond ACK based upon traffic condition 。 Configurable Flow Control Credit to balance bandwidth utilization and buffer usage
Transaction Layer 。 Packet forwarding options including Cut-Through and Store & Forward 。 Support up to 512-Byte Max Payload Size 。 Low packet forwarding latency < 150ns (typical case) 。 Access Control Service (ACS) for peer-to-peer traffic 。 Address Translation (AT) packet for SR-IOV application 。 Support Atomic operation 。 Support Multicast 。 Provide Performance Visibility for ingress/egress packet types and packet counts
Dual-Host Application 。 Support one Cross-Domain End-Point (CDEP) port for Host-to-Host Communications 。 Support Fail-over using CDEP port 。 Provide up to 4 physical or 8 virtual DMA channels enabling communications among Hosts and EPs
Reliability, Availability and Serviceability 。 Enhanced Advanced Error Reporting 。 End-to-End Data Protection with ECC 。 Error Handling Mechanism 。 Support Surprise Hot Removal 。 Support Downstream Port Containment (DPC) 。 Support Hot Plug for Upstream and Downstream port 。 Provide Serial and Parallel Hot Plug Types 。 Support LED Management 。 Thermal Sensor reporting operational temperature instantly 。 IEEE 1149.1 and 1149.6 JTAG interface support
Advanced Diagnostic Tools - PCIBUDDYTM 。 PHY EyeTM 。 MAC ViewerTM (including embedded LA) 。 PCIEditorTM 。 On-Line PRBS loopback test 。 On-Line Compliance pattern test
Standard Compliance 。 Compliant with PCI Express Base Specification Revision 3.1 。 Compliant with PCI Express CEM Specification Revision 3.0 。 Compliant with Advanced Configuration Power Interface (ACPI) Specification 。 Compliant with System Management (SM) Bus, Version 2.0
Power & Package 。 Typical power consumption: 2.9W (full-loading at Tj=80℃) 。 Totally Lead-Free & Fully RoHS Compliant 。 Halogen and Antimony Free. “Green” Device 。 For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/ 。 Packages: 196-pin HFC 15mm x 15mm package