Next Generation HiFlex? Ethernet Network Clock Generator
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The PI6LC48S25B is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25MHz crystal input, while the PLL loop is used to generate the 156.25MHz and other Ethernet clock frequencies. An additional buffered crystal oscillator output is provided to serve as a low noise reference for other circuitry.
For Ethernet applications other than 10GbE, programmable dividers allow for simultaneous output of 312.5, 156.25, 125, 100, 50, and 25MHz. This device offers both pin selection and I2C interface to give more options to meet various system needs.
| Compliance (Only Automotive(Q) supports PPAP) | Standard |
|---|---|
| Supply Voltage (V) | 2.5, 3.3 |
| Additive Jitter (ps) | 0.3 |
| Skew (PS) | 0 |
| Maximum Output Frequency (MHz) | 25/ 50/ 100 / 125/ 156.25/ 312.5 |
| Input Type(s) | Crystal, CMOS, Differential |
| Output Type(s) | LVCMOS, LVPECL, LVDS |
| Number of Outputs | 11 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
| Supported Frequencies (MHz) | N/A |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2328 | 2018-04-12 | 2018-10-12 | Device End of Life for tray packaging only |
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
