Fibre Channel Clock Generator
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The PI6LC48P02 is a 2-output LVPECL synthesizer optimized to generate Fibre Channel, Ethernet and storage reference clock frequencies and is a member of Diodes' HiFlex family of high performance clock solutions. Using a 26.5625MHz crystal, the most popular Fibre Channel (FC) frequencies can be generated based on the settings of 2 frequency select pins. Using 25MHz Xtal, most Ethenrnet frequencies inckuding 100MHz can be generated, while using 26.041667MHz Xtal, 156.25MHz can be generated for Networking applications.
The PI6LC48P02 uses Diodes' proprietary low phase noise PLL technology to achieve ultra low phase jitter, it is ideal for Networking, data center, and storage systems.
Compliance (Only Automotive(Q) supports PPAP) | Standard |
---|---|
Supply Voltage (V) | 2.5, 3.3 |
Jitter RMS (ps) | 0.35 |
Skew (PS) | 0 |
Output Frequency (MHz) | 2x 106.25/ 212.5/ 159.375 MHz |
Input Type(s) | Crystal, CMOS |
Output Type(s) | LVPECL |
Number of Outputs | 0 |
Ambient or Junction Temperature (°C) | -40 to 85 |
Supported Frequencies (MHz) | 106.25, 212.5, 159.375 |
Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents
PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs. HiFlex Clock FInder tool
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.