3.3V, Low Skew LVTTL/LVCMOS to LVDS Fanout Buffer
Log in or register to manage email notifications about changes to datasheets or PCNs for this part.
The PI6C48545 is a high-performance low-skew LVDS fanout buffer. PI6C48545 features two selectable single-ended clock inputs and translate to four LVDS outputs. The CLK0 and CLK1 inputs accept LVCMOS or LVTTL signals. The outputs are synchronized with input clock during asynchronous assertion/deassertion of CLK_EN pin. PI6C48545 is ideal for single-ended LVTTL/LVCMOS to LVDS translations. Typical clock translation and distribution applications are data-communications and telecommunications.
| Compliance (Only Automotive Supports PPAP) | Standard |
|---|---|
| Function | Buffer |
| Number of Outputs | 4 |
| Output Type(s) | LVDS |
| Maximum Output Frequency (MHz) | 650 |
| Additive Jitter (ps) | 0.05 |
| Supply Voltage (V) | 3.3 |
| Input Type(s) | LVTTL, LVCMOS |
| Skew (ps) | 40 |
| Ambient or Junction Temperature (°C) | -40 to 85 |
Something went wrong with your request. Please try again later. If this problem continues, please contact Diodes support for assistance.
