3.3V, Low Skew LVTTL/LVCMOS to LVDS Fanout Buffer
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The PI6C48545 is a high-performance low-skew LVDS fanout buffer. PI6C48545 features two selectable single-ended clock inputs and translate to four LVDS outputs. The CLK0 and CLK1 inputs accept LVCMOS or LVTTL signals. The outputs are synchronized with input clock during asynchronous assertion/deassertion of CLK_EN pin. PI6C48545 is ideal for single-ended LVTTL/LVCMOS to LVDS translations. Typical clock translation and distribution applications are data-communications and telecommunications.
Compliance (Only Automotive Supports PPAP) |
Standard |
|---|---|
Function |
Buffer |
Number of Outputs |
4 |
Output Type(s) |
LVDS |
Maximum Output Frequency (MHz) |
650 |
Additive Jitter (ps) |
0.05 |
Supply Voltage (V) |
3.3 |
Input Type(s) |
LVTTL, LVCMOS |
Skew (ps) |
40 |
Ambient or Junction Temperature (°C) |
-40 to 85 |
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A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.
| PCN # | Issue Date | Implementation Date | Subject |
|---|---|---|---|
| PCN-2770 | 2025-10-30 | 2025-10-30 | Add Fab Site Code, Country of Diffusion (COD) and Assembly Site Origin (ASO) on Product and Shipping Labels for all Diodes Products |
