HiFlex时钟产生器结合了最佳的规格弹性与业界最好的抖动性能，可以满足需要最佳时钟解决方案效能的应用。一个独立的HiFlex时钟产生器，在一个芯片中，结合了多个时钟与缓冲器的功能，可以支持广泛的时钟频率，同时减少需要空间的要求以及BOM的成本。Diodes 的HiFlex时钟可以产生讯号抖动最低0.3ps (RMS)与最高频率到625MHz的时钟讯号。HiFlex时钟可以轻易设定，输出多种时钟频率和输出类型。HiFlex时钟产品系列可以完美应用在网络与电信等需要高性能时钟产品的应用。
Pericom PLL automatically shuts down when the input clock is from several MHz to 20MHz. The actual values depend on the specific product. Lower frequencies will results in higher jitter. Please check with the datasheet or contact technical support: http://www.pericom.com/support/contact-pericom-support/
The PI6C24xx family are capable of supporting spread spectrum. The PI6C24xx family has a SSC spread of + / - 0.5% with modulation frequency of 33KHz.
The PI6C25xx family are capable of supporting spread spectrum. The PI6C25xx family has a SSC spread of + / - 0.5% with modulation frequency of 33KHz.
Although the datasheet mentioned that it is only for test purposes, there should be no problem to use the bypass mode in a real application. In bypass mode, the PLL will be off and the clock device will function as a normal clock buffer with delay.
To interface a single-ended signal to a differential driver, connect the single-ended signal to one of the differential input of the driver. The second differential input should be connected to VDD/2. If no VDD/2 source is present, use a voltage divider circuit. See Application Note 56.
Pericom offers two options in the SuperClock family. One has a suffix with a letter “A” and one without. The part number with letter “A” suffix has 4Qx falling edge aligned with the 3Qx rising edge, similar to other vendors. The part number without the letter “A” suffix has 4Qx rising edge align with 3Qx rising edge.
Devices that support industrial temperature will be specified in the datasheet to support a temperature range of -40C to +85C. For commercial temperature range, the datasheet will specify that the device supports temperature ranges of 0C to +70C.
Our PLL clocks will lock within a few milliseconds or less.
Input pins should never be left open or floating. The system may false trigger from noise if the inputs are left floating. It is recommended that all unused input pins be tied to a valid logic level using a resistor. The advantage of using pull-up or pull-down resistors is that they ensure a defined logic levels when the bus is floating. Typical resistor values range from 1 k-ohm to 10 k-ohms. Outputs may be left floating.
Yes, LVPECL and PECL can interface with each other. However, sometimes a resistor network is required to adjust the common mode voltage. See Application Note No. 7.
Unlike other competitors, Pericom's SuperClocks have no issues with power sequencing.
It is recommended, but not required to have a dedicated AVcc power plane. It is also recommended to use wide trace for power and ground signals.
Not all obsolete parts will have a direct replacement. However, we recommended that you contact your regional sales office.
The output-to-output skew is typically 250ps or less on the same device unless otherwise specified on the datasheet.
R(out) data can be found in the IBIS model located under "pull up" and "pull down". Data should be taken at ~1V and using the equation Rout=V/I.
Jitter can be cause by: poor decoupling to the Vcc and GND, signal source with heavy jitter, slow edge rate which will provide additional time to introduce jitter to the signal. Additional information can be found in Application Note 24: Designing for Minimal Jitter when using Clock Buffers
There are several types of jitter, but the main ones are: cycle-to-cycle jitter, period jitter, half period jitter, and peak-to-peak jitter. Jitter terminology can be found in AB36: Jitter Measurement Techniques at Application Brief No. 36 or Application Note No. 27.
In bypass mode, the PLL is shut off; therefore there is no need to connect the FB loop. It can be left floating or used as an extra output.
Cycle-to-cycle jitter is the difference in the clock's period between two consecutive cycles and is expressed in units of + pico-seconds. This is because it can be either leading or lagging from the ideal output waveform.
Half-Period Jitter is the measure of maximum change in a clock's output transition from its ideal position during one-half period. It is measured as: tjit(half-period) = thalf-period n – 1/2 ƒo, where ƒo is the frequency of the input signal.
PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs. HiFlex Clock FInder tool
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
Unused output can be left floating. However, it is recommended that the input pins are either tied to VCC or GND with a 1 k-ohm to 10 k-ohm resistor to prevent any unknown states.
The correct capacitor depends on the actual feedback trace. Typical design uses feedback capacitor in the range of 0pF to 12pF.
The PI49FCTxx suffix is reversed on package top mark, but it is the same part. For the PI49FCTxx, there are usually three additional letters. They are the speed grade, package type, and the part number codes. A detailed explanation can be found Here.
ICC value will change with frequency and loading. As frequency increases, the ICC value will also increase. This trend also applies to loading. As loading increase, ICC value will increase.
All Pericom's products that are not lead-free are composed of 85% Sn and 15% Pb. For lead-free products, they are composed of 100% matte Sn. Lead-free products are marked and ordered with the letter "E" suffix at the end of the part number.
A, B, C, D and Blank indicate the speed grade specified on the datasheet. Typical operating frequency for these speed grades are as followed: A:33MHz, B:66MHz, C:80MHz and D: 133MHz.
Output impedance is the resistance between the NMOS and Ground when the device is driving low and the resistance between the PMOS and Vcc when the device is driving high. The driver strength is inversely proportional with output impedance. A lower output impedance will result in higher driver strength.
Some of Pericom's PLL's have the output oscillate for a short period of time (around 5ms) when the input signal is removed. But it will eventually settle down to a DC low or a DC high.
The most ideal is to have as minimal input jitter as possible since the input jitter will contribute additional jitter to the output.
The value of the termination resistor depends on the output impedance of the device. It must meet the equation: Zo + Zseries = Ztrace
We recommend following JEDEC recommendation by using the following filter circuit for AVcc: place the 2200pF capacitor close to the PLL, use a wide trace for the PLL analog power and ground, connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL), and recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8-ohm DC max, 600-ohm @ 100MHz).
For reflow and soldering temperature information, please visit Pericom's Quality webpage.
FIT and MTBF data can be found at Pericom's Quality webpage.
Lead (Pb)-Free and Green information can be found on individual datasheets or Pb-Free & Green Page.
Pericom does not have any thermal data relating to the board or case. Other quality information can be found at Quality Page.
Sometimes the speed grades and the package nomenclature for our FCT devices may be swapped around. Full explanation for nomenclature information can be found here, under “Packaging Support Documentation”.