By: Chris A. Ciufo, Editor-in-Chief, Embedded Systems Engineering
Clock jitter can adversely affect high-speed protocols such as Ethernet, PCI Express and USB 3.0. You can calm your system down knowing these three simple points.
Timing is everything, which is why jitter skews everything up. Jitter is the difference between expected and actual timing edges in a system; the worse it becomes—the more adversely it affects your system (Figure 1). Jitter is proportional to lower voltage thresholds, directly proportional to clock frequency, and a major source of bit error rate (BER) in high-frequency GHz systems.
In this short primer we’ll:
Figure 1: Jitter as the clock phase shifted from its expected position.
Point #1: High-performance signals require low jitter at receivers.
Digital systems require high precision clock sources from either crystals or crystal oscillators. 40 Gb Ethernet, for example, requires a clock source with under 0.3ps of jitter. When there’s jitter in the reference clock, it’s amplified by clock timers and PLLs in the PHY (Figure 2), since the phase lock loop responds to the clock edges.
An out-of-phase clock can often skew a GHz signal beyond an acceptable spec at the receiving end. The higher the data rate, the more accurate the source timing source must be. That is: as data rates increase, the jitter requirements tighten.
Figure 2: Jitter is amplified by clock timers and PLLs, compounding the problem.
Lower jitter means lower BER, and lower BER is better. Improving jitter lowers BER because at the receiving end, the Rx circuitry must recover the transmitted clock from the bit stream by: 1) knowing when to sample the bit stream; and 2) determining if the data represents a “0” or a “1.” The encoded bit clock determines when the receiving data is to be sampled; if the clock is phase-shifted due to jitter, the receiver may sample the bit stream at the wrong time, which results in bit errors.
Point #2: Start with a low-jitter clock source at the transmitter.
If GHz signals like HDMI (~ 10 Gbits/s) or USB 3.0 (5 Gbits/s) require low jitter at the transmitter, the best way to reduce source jitter is to start with an ultra “clean,” low-jitter clock source.
While jitter has many possible sources at the transmitting end, the biggest “bang for the buck” can be achieved through the source clock. A high-quality clock source may widen the jitter margin of the system (“system” = source, Tx, link, Rx), reducing the need for extended and excruciatingly complex engineering effort to reduce second- and third-order jitter sources like cross-coupled traces or inducted skin effect in PCBs.
Figure 3 shows a crystal oscillator demo board from Pericom Semiconductor with a 156.25 MHz XO source. The XO populated on this board is spec’d having a maximum RMS jitter of 0.2ps—30 percent lower than that required by 40 Gb Ethernet, giving a comfortable Rx margin on an Ethernet link.
How about in actual practice? Using an Agilent phase noise analyzer and a LeCroy 6 GHz scope, the XO exhibits a real-world jitter of 0.11 ps, which is well below that required by 40 Gbits/s Ethernet (Figure 4). This low-jitter clock source means that other components in the system can inject nearly 0.2ps additional jitter before the link jitter becomes out of spec (and out of an acceptable BER range). Clearly, starting with a low-jitter clock source gives a GHz system designer more breathing room in a design.
Figure 3: The UX704 demo board from Pericom Semiconductor is useful for demonstrating a low-jitter clock source. (Courtesy: Pericom Semiconductor.)
Point #3: Know how to use the XO in a system.
A typical GHz system is shown in Figure 5. Here, an ultra-low jitter XO feeds a clock buffer that provides multiple clocks for a variety of GHz devices, including a 40 GbE PHY, an Ethernet switch and a ternary content addressable memory (TCAM), part of a layer 3 router. Pericom’s UX7 series XO is the heart of the low-jitter system, and is capable of approximately 0.1ps (RMS) jitter between 12K – 20 MHz as Figure 4 shows.
Figure 4: Using a phase noise analyzer by Agilent (top) and a LeCroy 6 GHz scope (bottom), the jitter of the demo board from Figure 3 is shown to be 0.111 ps (shown as 111.949 fs).
To avoid using multiple XOs in a system, the PI6C49S1510 clock buffer can provide up to 10 output clocks (three are shown in Figure 5), with a very low additive jitter of 0.03ps—essentially replicating the XO’s low jitter to all of the outputs. Figure 6 is a screenshot of the same bench test as Figure 4 but at an output downstream of the clock buffer. Note the total RMS jitter of the XO plus buffer is only 0.15 ps
Figure 5: A typical low-jitter system starts with an ultra-low-jitter XO. (Courtesy: Pericom Semiconductor.)
RMS. For convenience, both the XO and the clock buffer run on 2.5 or 3.3VDC, further simplifying designs.
Figure 6: The total jitter of the notional system shown in Figure 5 using Pericom demo boards in the same bench set-up as Figure 4. Total additive jitter is a mere 0.15 ps (RMS).
XO and Buffer All-in-One
Another way to create low-jitter systems besides what’s depicted in Figure 5 is to use. Pericom’s FlexOut clock generator, which combines an XO and clock buffer into a single package. The frequencies involved and the need for ultra clean (low-jitter) clocks, are the reasons the FlexOut PI6CXG05F62a has an even lower jitter spec than the previously described XO (~0.1ps [typical]/0.15ps [max] from 12K – 20 MHz) and supports up to six outputs in LVPECL and LVDS configurations
No external XO is needed (that’s the whole point!), and neither XO trace terminations nor XO power filters are required. This device uses Pericom’s proprietary quartz timing source with a special clock IC shrunk into a small LQFP package that’s smaller than the two devices it replaces.
Regardless of which architecture a designer uses—XO alone, XO plus clock buffer, or a fancy combo device like the FlexOut—low BER GHz systems require low jitter. Starting at the transmitter, right at the clock source.