Protocol-agnostic Signal Switches Simplify Designs
Chris A. Ciufo, Editor-in-Chief, Embedded; Extension Media
From PCIe to HDMI to DDR3, good quality signal switches can route your data and simplify designs—if you know how to use them.
The simplest way to route signals to two or more nodes on and between circuit boards would be to use direct copper wiring: traces, cables and edge or riser connectors. But high-speed signals for DDR3/4, PCI Express 2.0/3.0, HDMI, DVI, USB 3.0 and others are all in the gigahertz range and don’t take kindly to this kind of “direct” routing.
Figure 1: A generic 2:1 signal switch that connects U1 to either U2 or U3. This example is shown for PCI Express, but would look identical for any type of signals.
A variety of signal integrity (SI) issues arises—from impedance mismatch to crosstalk and more—necessitating the use of signal switches to facilitate these kinds of multi-point connections. In this article we’ll examine several simple examples of where signal switches simplify designs and protect the signal integrity of multi-gigabit transmissions.
Switches are MUXes
The 2:1 digital switch in Figure 1, while shown for a PCI Express implementation, is actually protocol agnostic in that it matters not what communications protocol, packets or frames are passed between the ports. Its primary job is to connect U1 to either U2 (Chipset A) or U3 (Chipset B) at gigahertz speeds. This kind of switch is a signal switch, and it’s important to differentiate it from a packet switch.
Packet switches route packets (a higher level than just electrical signals) between the ports and depending upon the interface type, the switch might perform bridging or routing. That is, they often make routing decisions based upon the packets (header information), and are optimized for the type of packets being routed such as PCIe, USB, Thunderbolt and so on.
Packet switch interfaces and I/O match the standard to which they’re switching, such as PCI Express or XAUI, and follow the rules of the standard. For example, PCIe switches worry about things like root complexes and PCIe endpoints. Conversely, signal switches don’t care about these things. One other key distinction between packet and signal switches: packet switches are often overkill and more costly in many switching applications.
Signal Integrity Cannot Be Ignored
As described above, high-speed signals now routinely operate at RF frequencies, causing copper PCB traces, board interconnects, cables and even IC pins or balls to act like antennae. Look at these speeds: PCIe Gen 1 is 2.5 Gbps, Gen 2 is 5 Gbps, and Gen 3 is 8 Gbps. DRAM like DDR3/DDR4 moves data at up to 3.200 GT/s. USB 3.0 is up to 5 Gbps, and 10Gig Ethernet is notionally 10 Gbps. For these specs and more, the top end is in the 8-12 Gbps range.
Switches are part of the overall channel along which signals travel from source to destination. SI through switches cannot be ignored, but it’s useful to take a look at the channel, too.
From the signal’s source (say, a PCIe root complex) to the destination endpoint, gigabit signals will degrade along the channel (transmission line losses) due to:
- the channel material (Al, Cu, alloy, solder, etc.)
- dielectric losses around the channel
- cross coupling with other channels
- buried PCB vias and stubs
- discontinuities such as connectors or signal switches
- different channel materials interconnected together
- other third- and fourth-order effects that become significant at these frequencies
The switch, which will become a part of the channel, is characterized by:
- off/on isolation
- insertion loss
- return loss
- switch enable/disable time
- bandwidth through the channel and its various elements
Application 1: PCI Express Lane and Slot Expander
The 2:1 switch scenario shown in Figure 1 has applicability in many embedded designs. In one case the switch device allows switching to a second slot peripheral such as a storage device or co-processor. In the other case, an auxiliary peripheral such as a graphics card can be added to supplement (or replace) the main graphics card. Although these examples imply peripherals plugged into connectors, that need not be the case—the peripherals can be ICs soldered to the main board but enabled by the switch.
Figure 2 shows the redundancy set-up, which is nothing more than a switchable fanout improvement from the PCIe root complex U1. The switch selects either J1 or J2. Although we’ve suggested this is a redundancy application, it also describes the case where the root complex doesn’t have enough lanes to connect to devices in J1 and J2 simultaneously. The host CPU tells the switch which slot (or peripheral) to connect to U1 on the fly.
Figure 2: The signal switch, shown here in a PCIe example, connects the root complex to one of two slots (or one of two peripherals). This might be a redundant system, or the switch increases the root complex’s fanout by making it appear to offer double the number of lanes to the system (not simultaneously).
In another variation, Figure 3 shows an Intel® Sandy Bridge CPU (2nd generation Core™ architecture) supporting a total of 16 PCIe outputs (x16). By inserting a high-performance signal switch in the middle of 8 of the 16 lanes, the option exists to add a second x8 graphics card or peripheral. So the system can provide x16 to one slot/peripheral, or x8 to two slots/peripherals.
Figure 3: A high-performance signal switch capable of switching at 8 Gbps PCIe speeds bifurcates 16 lanes and provides the option of adding one (x16) or two (x8) graphics cards. This approach allows for either a slot expander or flexible fanout to onboard components.
The switch listed—a Diodes Incorporated PCIe 3.0 2-lane, 4-channel 2:1 switch—offers routing and component flexibility. Of course, without the switch, the designer could have routed x8 to each of two devices or slots, but there would be no option to send all 16 lanes to the upper graphics card should that need arise.
There’s another variation on this, too, where a design has only two root complexes but needs to flexibly aggregate them to two slots or peripherals. This switchable redundancy is shown in Figure 4.
Figure 4: Yet another variation on the configurations from Figures 2 and 3, this architecture shows redundancy for fail-safe systems. Diodes Incorporated devices for this set-up are indicated.
Signal Integrity Issues
We’ve described three simple switch scenarios that offer significant benefits to designers. Not a one of these would have worked by merely connecting PCB traces without a signal switch. Why? The multi-drop connections and unequal traces caused by direct connections would, at the very least, cause impedance mismatch resulting in wave reflections on rising/falling signal edges. These reflections degrade the channel substantially. These SI problems increase bit error rate (BER) most likely to the point of slower speeds or a completely closed signal diagram “eye” and a PCIe system that doesn’t work.
According to Diodes Incorporated application engineer Paul Li, the “velocity of the signal on the FR4 PCB is about 5 inches per 1 ns, [and] the “knees” caused by a 1-inch sub-trace are 200ps.” Added together, rising and falling edges of any PCIe signal in a direct-connect system are over 400ps, which will corrupt a PCIe signal transmission with a 400ps duration (which is most of them!).
Companies like Diodes Incorporated carefully optimize their signal switches to maximize data throughput through the switch itself (without causing the reflections described above), achieving up to 11 GHz bandwidth—more than ample for the 12 Gbps maximum of every current-generation serial communications standard (6 GHz rising/falling edges). Diodes' follows the industry-standard convention of quoting maximum speed (11 GHz) at 3 dB insertion loss. Most industry signal switches top out at 8 GHz.
How is this performance achieved? The company won’t say, other than to describe a patented “highly-tuned architecture using NMOS and PMOS transistors with supporting circuits and neighborhood elements” that reduces high frequency loss. Most of the company’s switches are in either 0.18 or 0.13 micron geometry, with MOSFET transistor sizes optimized to balance capacitance (not too much to lower data frequency), voltage (enough to drive output lines) and cost for customer designs.
Application 2: Memory Bank Switches
Not all of today’s CPUs can directly access as much memory as some systems require, or alternatively, some systems such as radar require wider memory widths than what the processor can deal with. There’s also a use case where a different width memory module needs to be “ganged” to increase the width or depth. Also, there are cases like in Non-Volatile DIMM (NVDIMM) modules where DDR3 or DDR4 data need to be preserved during power shut down by transferring its contents to NAND Flash. All of these scenarios can use a signal switch. Figure 5 shows some details for a Diodes' switch (PI2DDR3212).
Figure 5: Using a 2:1 MUX to expand memory banks.
We already know that speed is essential: these systems can run up to 2.133 Gbps for DDR3-2133 and 3.200 Gbps for DDR4-3200. The set-up in Figure 5 requires 12 switches per module, leading to a 12/14 channel 2:1 MUX/DeMUX signal switch like Diodes' PI2DDR3212 (Figure 6). Let’s drill down into the parameters shown in Figure 6.
Figure 6: Important signal integrity (SI) details of a 2:1 MUX used for the Figure 6 architecture.
Insertion loss: describes the attenuation caused by inserting the switch into the signal path. A smaller number (larger negative dB) is better for the overall system loss budget and outstanding value of -0.7 dB at rates up to 2.00 Gbps. (For the PCIe switch described above, Diodes' achieves -1.3dB @ 4GHz (8Gbps) which is also very good since insertion loss increases with frequency.)
Return loss: describes the waveform attenuation caused by reflections when the switch is inserted in the signal path. Samtec, a respected industry connector supplier and author of many reference materials on signal integrity, recommends return losses of less than -10dB. This switch’s -23dB is excellent.
Crosstalk: indicates induced signals (and losses) from adjacent lines, channels, pins and connector blades. Here we see -25dB @ 4 Gbps where the larger the absolute value of the number, the less crosstalk and jitter are present in the switch. This leads to a wider eye diagram, lower BER, and all around better SI and data performance.
Bit-to-skew and channel-to-channel skew: are measures of how the signal low-to-high and high-to-low transitions for each bit vary per cycle and between channels on multi-channel switches. The target is a symmetric rise/fall waveform which, according to Diodes' “doesn’t eat into the timing budget for an eye opening.” The 20 ps max reported for this device is very good.
Other parameters like Low off isolation, Low switch enable, and Low switch disable are measures of wave reflections when the switch is off and how long it takes the switch to turn on or off, respectively. Since signal switches can be enabled in real-time in the scenarios described in this article, it’s essential for them to operate very quickly.
A Switch In Time
As we’ve seen, signal switches differ from packet switches in their simplicity and cost, yet both offer the ability to simplify system designs, increase fanout, and provide functionality. Yet at multi-gigahertz speeds, switches must be as near lossless as possible, minimize signal losses and maximize SI. Switches from Diodes' come in more flavors and configurations than could possibly be described here. For more information, check out the company’s website link here.
This article is sponsored by Diodes Incorporated