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Diodes Pericom: A product line of Diodes Incorporated

Pericom Product Change Notices

PRODUCT CHANGE NOTICE (PCN)
PCN procedure.pdf 

 

PCN # Implementation Date Subject
16-19 2016-09-06
16-12 2016-09-09 Adding two internal assembly and test sites: Diodes Technology (Chengdu) Company Limited (CAT) located in Chengdu, China and Diodes SKE/DSH (Shanghai Kaihong Electronic Co./Diodes Inc. Shanghai) (SAT) located in Shanghai, China.
16-07 2016-08-31 Die revision of PI3V312 will be upgraded to support broader application.
16-08 2016-05-20 Update some of our package outline drawing dimensions to align with JEDEC standards (with some exceptions) on few packages to accommodate the POD’s of our existing assembly suppliers and own assembly factories
16-11 2016-08-25 Change in the Pin 1 Tape and Reel orientation for Pericom’s package code ZE10 (TDFN 10 Pin package) to comply with the current EIA surface mount component handling Standard (EIA-481-D).
16-03 2016-06-21 Die change to eliminate three errata's in previous silicon.
16-06 2016-06-18 Add an extra bonding wire of Pin 9 (“NC”) to expand the test coverage for PI5USB2544ZHEX and PI5USB2544AZHEX
16-04 2016-06-01 Porting some RTC products from CSMC 0.5 micron, 5-volt CMOS process to previously qualified MagnaChip’s foundry
PCN # Implementation Date Subject
15-16 2016-01-06 Porting from MagnaChip's Fab 2 to Fab 3 and converting some products from Au to Cu wire
15-07 2015-11-04 Porting from MagnaChip's Fab 2 to Fab 3 and converting some products from Au to Cu wire
15-05 2015-04-04 Datasheet parameter change.
15-04 2015-05-11 packing method has been changed for these packages from tubes to tray: ZD48, ZF36, ZF56, ZH42.
PCN # Implementation Date Subject
14-29 2015-03-24 Porting some bus switch products from Global Foundry 0.5 micron, 5-volt CMOS process to previously qualified MagnaChip.
14-25 2015-02-11 Pericom would like to notify all customers that Global Foundry Fab 2 is obsoleting their 0.5 micron technology. To continuously support orders, Pericom decided to port some clock products to previously qualified MagnaChip’s foundry using the same process.
14-24 2015-01-10 Internal wire bonding layout for PI7C9X113SLFDE and PI7C9X118SLFDE.
14-19 2014-12-12 Add Nantong Fujitsu Microelectronics Co. Ltd. (NFME) as approved vendor listing for IC products in the QSOP, TSSOP, MSOP, QFN and LQFP packages.
14-21 2014-12-03 Die change for products PI7C9X2G303ELA / PI7C9X2G304SLA / PI7C9X2G404SLA
14-20 2014-11-25 Die revision for PI7VD9004ABHFDE to fix / improve issues found in certain systems.
14-14 2014-07-14 Reinstate PI6C557-06 product in TSSOP (L) package
14-15 2014-09-25 Porting some remote controller products from Global Foundry 0.6 micron CMOS process to previously qualified MagnaChip’s foundry using 0.5 micron CMOS as Global Foundry Fab 2 is obsoleting their 0.5 and 0.6 micro technology.
14-13 2014-09-30 Porting PI5A124TEX from Global Foundry 0.5 micron, 5-volt CMOS process to previously qualified MagnaChip
14-11 2014-07-30 Porting some bus switch products from Global Foundry 0.5 micron, 5-volt CMOS process to previously qualified MagnaChip.
14-08 2014-05-20 Transferring CJE’s S24 and S20 packages to halogen-free BOM (Bill of Material) since the volume of of non-halogren-free BOM is decreasing rapidly and will be obsolete soon
14-01 2014-02-28 Porting some bus switch products from Global Foundry (C) to MagnaChip (G) using the same process with layout optimization.
PCN # Implementation Date Subject
13-25 2014-01-28 Add Nantong Fujitsu Microelectronics Co. Ltd. (NFME) to PTI approved vendor listing for IC products in the SOIC packages.
13-24 2014-01-10 Jiangsu Changjiang Electronics Technology Co., Ltd., (CJE) SOT-23 package will be moved from C3 plant located in Jiangyin, Jiangsu China to C9 plant in Chuzhou, Anhui China

12-27.A 2013-09-06 Amended PCN # 12-27 which states that these packages: TSSOP (L08, L14, L16) and QSOP (Q16) will be assembled using copper wire. Pericom has changed the business plan and we now intend to use gold wire only for particular products while the rest remains using copper wire.
13-04.A 2013-09-06 Amended PCN # 13-04 which states that these packages: TSSOP (L08, L14, L16, L24), SSOP (H20), QSOP (Q16, Q20, Q24), SOIC (W08, W14, W16) and TQFN (ZL72) will be assembled using copper wire. Pericom has changed the business plan and we now intend to use gold wire only for particular products while the rest remains using copper wire.
13-14 2013-10-11 Porting some MPS products from CSMC (W) to MagnaChip (G). Layout optimization was also done without major die re-design.
13-09 2013-10-01 Revision of PI3CHxxxxx will be upgraded to support broader application. We also would like to reactivate the obsolete parts using the new die and copper wire.
13-11 2013-04-22 New silicon revision to fix errata on PI7C9X130BNDE
13-04 2013-04-24 Copper wire qualification for copper bond wire process for various TSSOP (L08, L14, L16, L24), SSOP (H20), QSOP (Q16, Q20, Q24), SOIC (W08, W14, W16) and TQFN (ZL72) packages at Greatek assembly site.
13-02 2013-04-16 Porting some MPS products from CSMC 0.6 micron, 5-volt CMOS process to previously qualified MagnaChip’s foundry using 0.5 micron, 3.3-voltage CMOS process. Layout optimization was also done without major die re-design.
PCN # Implementation Date Subject
12-27 2013-01-28 Copper wire qualification for copper bond wire process for various TSSOP (L08, L14, L16) and QSOP (Q16) packages at CJ assembly site.
12-28 2013-01-24 To align tape reel quantity with PSC
12-26 2013-01-05 Copper wire qualification for copper bond wire process for various TSSOP (L20, L28), TDFN (ZE10) and TQFN (ZA08) packages at Greatek assembly site.
12-22 2012-10-27 Adding ASE Electronics assembly facility in China (ASEN) to our qualified supplier list of approved IC package subcontract manufacturers.
12-21 2012-10-27 CJE’s assembly and test site will be moved from JiangYin, Jiangsu province, China to Chuzhou, Anhui province, China on the packages SOT23 (T03) , SC70 (C06/05/04/03), SOT143 (TB04), SOT89 (TD05/03), TO92 (NB) and TO94 (N) packages.
12-20 2012-10-23 Upgrade of PT8A2766 series to new version “V” to enhance anti-noise performance.
12-19A 2012-10-23 Copper wire qualification for copper bondwire process on SOT23 package (T3) at CJE assembly site completed.
12-13 2012-08-02 Porting PI3Cxxxxxx products from Global Foundry 0.5 micron, 3-volt CMOS process to MagnaChip’s foundry
12-12 2012-07-27 Enlarging the bond pad opening for PI5A3157CEX & PI5A3158ZAEX to improve the productivity in the wire bonding process with no change in the internal circuitry.
12-11 2012-07-22 Upgrade some Real Time Clock (RTC) products to new version “U” to enhance the timekeeping voltage range and power consumption performance
12-02 2012-01-23 Copper wire qualification for copper bondwire process for TSSOP-48 package (A48) at Greatek and OSE assembly sites.
12-03 2012-01-23 Copper wire qualification for copper bondwire process for LQFP packages (FD128 and FA48) at Greatek assembly site.
12-04 2012-01-23 Copper wire qualification for copper bondwire process for TQFN packages (ZL64, ZH42, ZH28, ZD20 and ZL32) at Greatek assembly site.
12-05 2012-01-23 Copper wire qualification for copper bondwire process for TQFN packages (ZB56) at Greatek assembly site.
PCN # Implementation Date Subject
11-19 2011-12-26 Copper wire qualification for copper bondwire process on ZD24, ZH20, FC64, FB48 and FD100 package types at Greatek and NJ100 at ASEM assembly sites completed.
11-20 2011-12-23 Porting some BUS Switch products from Global Foundry 0.5 micron, 3-volt CMOS process (C) to Magnachip (G). Layout optimization (shrink die) was also done without major die re-design
11-21 2011-12-23 Porting some BUS Switch products from Global Foundry 0.35 micron, 3-volt CMOS process (C) to Magnachip (G). Layout optimization (shrink die) was also done without major die re-design
11-18 2011-12-02 Copper wire qualification for copper bondwire process on FQFP and LQFP (MA208, MA128 and FG64) package at Greatek assembly site completed.
11-17 2011-11-19 Copper wire qualification for copper bondwire process on TQFN (ZF56, ZF32, ZH42, ZH32, ZD48) package at SPEL assembly site completed.
11-15 2011-10-19 Copper wire qualification for copper bondwire process on NB148 and NB160 packages at ASE Malaysia assembly site completed.
11-14 2011-09-20 Replace PI3EQX7712 series due to failed USB 3.0 Compliance - Change PN to PI3EQX7742STZHE
11-13 2011-09-01 Copper wire qualification for copper bondwire process on TQFN (ZB48) package at Greatek assembly site completed.
11-12 2011-05-23 Assembly suffix code change affecting PI6C4511WE and PI6C4512WE products
11-08 2011-05-14 Date Code format change for the TQFN (ZL) package from YW to YYWW for better readability. Will also include assembly and fab code for better traceability.
11-06 1969-12-31 MSL Level changed from MSL2 to MSL1 due to process improvement on TQFN-48 (ZB48) packages at Greatek.
11-05 2011-05-23 Copper wire qualification for copper bondwire process on LQFP (FF80) package at Greatek assembly site completed.
11-04 2011-05-18 Porting some BUS Switch products from Global Foundry (C) to Magnachip (G). Layout optimization (shrink die) was also done without major die re-design
11-01 2011-04-01 Die and Foundry change from Global Foundry (C) to Magnachip (G)
PCN # Implementation Date Subject
10-17 2010-12-23 Added a factory in Jinhua, China with an assigned factory code “E” as qualified manufacturing facility for our FCP products.
10-15 2010-12-12 Added a factory in Yantai China with an assigned factory code “N” as qualified manufacturing facility for our FCP products.
10-14 2010-11-09 Top mark for ZF56 package has been modified to remove the Country of Origin (COO).
10-13 2010-12-08 Adding the PSE Technology (Shandong) Corporation (aka:PSE-SD) located in the hi-tech zone of Jinan, Shandong, China as Pericom qualified manufacturing facility.
10-12 2010-12-02 Construction material change for the 49SNC, 49SAB, 49SUB series (GL) Quartz Crystal Series
10-04 2010-12-10 Copper wire qualification for copper bondwire process on ND256 package at ASEM assembly site completed.
10-03 2010-11-17 Removal of back mark
10-01 2010-04-18 Adding Changjiang Electronics Technology Co. (“CJ”) assembly facility in China to our qualified supplier list of IC package subcontract manufacturers.
PCN # Implementation Date Subject
08-02 2008-10-25 Die layout optimization that reduces chip size by » 25%, while using the same MagnaChip (previously known as Hynix) 0.5-mm wafer fab process and design rules.
PCN # Implementation Date Subject
07-02 2007-11-08 Product transferred from wafer fab vendor Taiwan Semiconductor Manufacturing Corp. (TSMC) Fab 7 (which closed operations during Q1, 2006), to their Fab 10 facility near Shanghai, China.
07-01 2007-08-16 Die layout optimization that reduces chip size by » 27%, while using the same MagnaChip 0.5-mm wafer fab process and design rules.
PCN # Implementation Date Subject
06-07 2007-01-12 Adding SPEL’s new package offering in this very thin dual and quad no-lead package types that have been previously qualified by other Pericom subcontractors.
06-06 2006-12-15 This product has been transferred from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to the previously approved CSMC-Tech, Wuxi, wafer fab in China.
06-05 2006-10-20 This product has been transferred from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to the previously approved CSMC-Tech, Wuxi, wafer fab in China.
06-04 2006-09-29 This product has been transferred from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to the previously approved CSMC-Tech, Wuxi, wafer fab in China.
06-03 2006-09-01 This product has been transferred from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to the previously approved CSMC-Tech, Wuxi, wafer fab in China.
06-02 2006-08-31 This product has been transferred from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to the previously approved CSMC-Tech, Wuxi, wafer fab in China.
06-01 2006-08-25 This product has been transferred from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to the previously approved CSMC-Tech, Wuxi, wafer fab in China.
PCN # Implementation Date Subject
05-22 2006-03-21 The change represents a die layout optimization that reduces chip size by » 27%, while using the same MagnaChip 0.5-mm wafer fab process and design rules.
05-21 2005-03-09 Moving closed CSMS Fab 1 product to already approved CSMS Fab 2.
05-20 2006-03-01 The change represents a die layout optimization that reduces chip size by » 40%, while using the same MagnaChip 0.5-mm wafer fab process and design rules.
05-19 2005-11-29 Immediate marking method change from labels to laser mark for select SaRonix FCP products.
05-17 2005-11-08 Pb-free / RoHS compliant version is phased in, effective immediately.
05-18 2005-11-08 Pb-free / RoHS compliant version is phased in, effective immediately.
05-16 2006-02-04 The change represents a die layout optimization that reduces chip size by approximately 27%, while using essentially the same 0.5-mm wafer fab process and design rules.
05-13 2005-09-25 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
05-14 2005-09-25 Ceramic package ceiling method is changing from glass frit (top/bottom half are ceramic material sealed by melting Pb-doped glass for hermeticity) to a seam seal (ceramic bottom half with a metallic stitch-welded for hermeticity .
05-15 2005-09-25 Ceramic package height is increasing from 1.15mm to 1.8mm.
05-12 2005-09-10 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
05-11 2005-08-06 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
05-10 2005-08-04 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
05-09 2005-07-22 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
05-08 2005-07-18 Product is transferring from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to previously approved CSMC-HJ wafer fab in China.
04-05 2004-06-04 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
05-07 2005-05-24 The change represents a die layout optimization that reduces chip size by approximately 25%, while using essentially the same 0.35-mm wafer fab process and design rules.
05-06 2005-05-17 Product is transferring from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to previously approved CSMC-HJ wafer fab in China.
05-05 2005-05-11 Product is transferring from approved wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1, to the already approved Fab 2 facility.
05-04 2005-04-28 Product is transferring from wafer fab subcontractor Chartered Semiconductor Manufacturing Singapore’s (CSMS) Fab 1 (which closed operations in March 2004), to previously approved CSMC-HJ wafer fab in China.
05-03 2005-04-14 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
05-02 2005-04-11 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
05-01 2005-04-04 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
PCN # Implementation Date Subject
04-17 2005-12-15 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
04-16 2005-01-27 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
04-15 2005-01-15 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
04-14 2004-12-21 The change represents a die layout optimization that reduces chip size by approximately 25%, while using the same 0.35-mm wafer fab process and design rules.
04-13 2004-11-20 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
04-12 2004-11-05 Moving these CSMS Fab 1 product to already approved CSMS Fab 2.
04-10 2004-09-18 The change represents a die layout optimization that reduces chip size by approximately 35%, while using the same 0.35-mm wafer fab process and design rules.
04-11 2004-09-18 The change represents a die layout optimization that reduces chip size by approximately 35%, while using the same 0.35-mm wafer fab process and design rules.
04-09 2004-09-08 Moving this CSMS Fab 1 product to already approved CSMS Fab 2.
04-08 2004-07-30 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
04-07 2004-07-08 Added them to Hynix’s standard CMOS 0.5 mm, 5 V 1P2M/1P3M process on their 200-mm wafer fab line.
04-06 2004-06-30 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
04-04 2004-06-04 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
04-01 2004-06-02 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.
04-03 2004-06-01 Addition of Hynix, Korea, as a wafer fab facility that can also manufacture our PI5C16862C Product, which is currently being built at TSMC in Taiwan.
04-02 2004-05-05 Moving these CSMS Fab 1 products to already approved CSMS Fab 2.