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The PI7C9X2G304EL is a PCI Express® 2.1 3-port/4-lane PCI Express ExtremeLo Packet Switch specifically designed to meet the latest low-power, lead (Pb)-free and green system requirements. The PI7C9X2G304EL is a high-performance, cost-effective solution that can be implemented in systems such as Embedded system, Wi-Fi router/ gateway, printer, storage, combo card, HBA, set-top box, motherboard, laptop, docking station, and other power-sensitive high performance platforms. The name of the family, ExtremeLo, refers to the proprietary power-saving PowerSave™ technology. The PI7C9X2G304EL provides one x1 or x2 upstream port and two x1 downstream ports. The PI7C9X2G304EL provides users the flexibility to expand or fan-out from a wide range of I/O Bridges such as PCH, ICH, IOH, embedded MCU, FPGA, and other Application Specific ICs.
Industry Specifications Compliance
PCI Express® Base Specification, Revision 2.1
PCI Express CEM Specification, Revision 2.0
PCI-to-PCI Bridge Architecture Spec., Rev 1.2
Advanced Configuration Power Interface (ACPI) Specification
PCISIG PCI Express 2.1 certificated
Integrated 100MHz Clock buffer for each downstream port
Reliability, Availability and Serviceability
Supports Data Poisoning and End-to-End CRC
Advanced Error Reporting and Logging o IEEE 1149.6 JTAG interface support
Link Power Management
Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power state
Active state power management for L0s and L1 state
Device State Power Management
Supports D0, D3Hot and D3Cold
3.3V Aux Power support in D3Cold power state
Supports up to 512-byte maximum payload size
Power Dissipation: 0.65 W typical in L0 normal mode Industrial Temperature Range: -40° to 85°C
MTBF: 50,927,360 hours
Package: 136-pin aQFN 10mm x 10mm
Pb free and 100% Green
Programmable Driver Current and De-Emphasis Level at each individual port
150ns typical latency for packet running through switch without blocking
Supports “Cut-through”(Default) as well as “Store and Forward” mode for switching packets
Advanced Power Savings
Empty downstream ports are set to idle
Clock to corresponding circuit is turned off when any port enters L1 or ASPM L1
Supports Access Control Service (ACS) for peer-to- peer traffic
Supports Address Translation (AT) packet for SR-IOV application
Supports Latency Tolerance Reporting (LTR) to improve Platform Power Management
Supports Optimized Buffer Flush Fill (OBFF) to improve Platform Power Management
Can I change Pericom packet switch's PHY parameters by EEPROM or SMBus?
Yes, all Pericom's packet switches provide EEPROM/SMBus to change PHY parameters including Low Driver Current, High Drive Current, Driver Transmit Current, De-emphasis Transmit Equalization, Receive Termination Adjustment, Transmit Termination Adjustment and Receiver Equalization Level Control.
Can I change Pericom packet switch's PHY parameters by strapping pin options?
Only GreenPacket Family packet switches, PI7C9X20505GP, PI7C9X20508GP, provide strapping pin option to change PHY parameters to improve signal quality. The following strapping pins are available: HIDRV, LODRV, DTX[3:0], DEQ[3:0], RXEQCTL[1:0], RXTERMADJ[1:0] and TXTERMADJ[1:0].
Do Pericom's packet switches accept reference clock source which is different from the root complex?
Yes, Pericom Packet Switches support operation in asynchronous mode, in which the reference clock source of Pericom packet switch is different from that of the root complex. However, the deviation in the clock signals must be within +/- 300ppm.
Do Pericom's packet switches require the device driver?
Yes, Pericom's Packet Switches require the standard PCI-to-PCI Bridge device driver in order to work, which is built in most of the OS's. That is, most of the OS's automatically install the standard PCI-to-PCI Bridge device driver when a Pericom's packet switch is plugged in the system for first time.
Do Pericom's Packet Switches Support Industrial Temperature Range (-40oC to +85oC)?
"YES, please refer to the following application notes.
AN219 – GreenPacket PCI Express Packet Switch – Industrial Temperature Support 1.0
AN220 – PI7C9X20303SL-404SL Industrial Temperature Support
AN221 – PI7C9X20303ULA Industrial Temperature Support"
Does Pericom provide a Compatibility Test List for the Packet Switches?
Does Pericom provide the design kits for packet switches and what information is included in the kit?
Yes, Design Kits for Packet Switches are available and include datasheet, product brief, reference schematics, software tools, demo board user manual, design guideline, IBIS file and related application notes. The design kits can be requested from your distributer or Pericom FAE.
Does Pericom provide the power consumption for the Packet Switches?
Yes, power consumption information is included in the design kit.
Does Pericom's packet switches support Hot-Plug feature?
GreenPacket Family (PI7C9X20505GP, PI7C9X20508GP) provides full support for hot plug functions, including Power Indicator, Attention Indicator, Attention Button, Presence Detected Changes, Slot Power Enable Power Fault. SlimPacket Family (PI7C9X20303SL, PI7C9X20404SL) and UltraLo Family PI7C9X20303UL only support Presence Detected Changes event. EEPROM or the strapping pins are used to enable the hot plug feature.
Does Pericom's packet switches support Spread Spectrum Clock (SSC) Sources?
No, Pericom packet switch does not support SSC sources.
How do I configure the configuration registers of Pericom's packet switches?
Pericom's packet switches can be configured by the configuration registers. There are three methods for this purpose: configuration read/write, SMBus, and EEPROM. Configuration read/write and SMBus can access configuration registers on-line. However, SMBus can only access these registers below 100H offset. Configuration read/write method is required if you intend to access registers above 100H offset. EEPROM can change the default values of certain configuration registers. EEPROM content is auto-loaded to packet switch when power-on.
How do I use SMBUS interface of Pericom's packet switches?
Please refer to the application note, "PCIe Packet Switch SMBus Programming Guild 0.1c" for detailed information. Please set SMBus address using GPIO[7:5]. Otherwise, SMBus may not work due to unknown SMBus address.
How to implement MRL_PDCx/PRSNTx pin?
The pin is name "MRL_PDCx" in GreenPacket Family packet switches and "PRSNTx" in SlimPacket Family and UltraLo Family with the same function. MRL_PDCx/PRSNTx pin is used to indicate whether a device is present in the slot of downstream ports in express card interface implemention. When MRL_PDCx/PRSNTx is asserted high, it represents the device is present in the slot of downstream ports. Otherwise, it represents the absence of the device. If express card interface is not implemented, MRL_PDCx/PRSNTx should be connected to GND through a pull-down resistor.
Is EEPROM required in the implementation?
The implementation of EEPROM depends on specific application. Normally, a packet switch is fully functional without EEPROM. However, in certain applications, EEPROM is needed to change certain default values of configuration registers. We recommend keeping the EEPROM footprint and circuitry just in case.
In order to meet the different application needs, the driving current and equalization of each transmitting channels can be adjusted individually using strapped pins (GreenPacket Family) and EEPROM (GreenPacket/SlimPacket/UltraLo Family). The driver current of each channel is set to 20mA in default mode without pins being strapped. To change the current value, the user can strap the pins/EEPROM either for nominal value (HIDRV, LODRV) or actual value (DTX [3:0]), which is a scaled multiple of Inom. The following tables illustrate the possible transmitted current values the chip provides.
What are the reasons that a Pericom's packet switch can not detect the plugging in of an endpoint in embedded system?
It is most likely that the boot code of the embedded system does not initialize Pericom's packet switch. The packet switch needs to be initialized in order to work normally. The packet switch is initialized by BIOS on x 86 systems and by the boot code on embedded system.
What are the reasons that Pericom's packet switch on an evaluation board can not detect an express card or a mini-pcie device?
The evaluation board of a Pericom's packet switch only provides the PCIe x1 slot on the downstream ports. Customers need an adapter they would like to plug in the express card or mini-pcie device. When the PRSNT# pin of the adapter is floating, the express card or mini-pcie card can not be detected.
What are the types of jitter?
There are several types of jitter, but the main ones are: cycle-to-cycle jitter, period jitter, half period jitter, and peak-to-peak jitter. Jitter terminology can be found in AB36: Jitter Measurement Techniques at Application Brief No. 36 or Application Note No. 27.
What is Surprise Hot Removal Function? Do Pericom's packet switches support it?
Surprise Hot Removal function allows unplugging of express card without prior notification. All Pericom's packet switches support this function. All downstream ports of SlimPacket Family and UltraLo Family packet switches support the surprise hot removal function. Only Port 1 and Port 2 of GreenPacket Family packet switches support this function. That is, only Port 1 and Port 2 of GreenPacket Family packet switches can implement the express card interface.
What is the lead finish for Pericom products? What about lead-free?
All Pericom's products that are not lead-free are composed of 85% Sn and 15% Pb. For lead-free products, they are composed of 100% matte Sn. Lead-free products are marked and ordered with the letter "E" suffix at the end of the part number.
What is the requirement of the reference clock of Pericom's packet switches?
The reference clock DC specifications and AC timing requirements are shown in the table below. More details can be found in "PCI Express Card Electromechanical Specification Revision 1.1", Chap 2.1.3.
Where can I find Mean Time Before Failure (MTBF) or Failures In Time (FIT) values for Pericom products?
FIT and MTBF data can be found at Pericom's Quality webpage.
Where can I find the information on your Pb-free and "Green" packaging?
Why is AC-Coupling required in the reference clock input pairs?
The reference clock input pins connect to external 100MHz differential clock. The signal must match to LVPECL or HCSL spec. A 100nF capacitor should be placed between the clock source and the packet switch. The purpose of this capacitor is to achieve AC coupling. This AC Coupling ensures the Packet Switch is compatible with the differential clock signals regardless the type of the clock. The input clock signals must be delivered to the clock buffer cell through an AC-coupled interface so that only the AC information of the clock is received, converted, and buffered. Please refer to the application note, "Express Interface AC-Coupling Application Note", in the design kit for more details.